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AURIX™ Forum Discussions

AURIX™ Forum Discussions

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User7559
AURIX™
I am trying to download a hex file using wiggler(JTAG)+memtool on a board made with AURIX 2G(SAK-TC397XP-256F300S BC)If I add a hex file after connect... Show More
User20578
AURIX™
I have 2 problems to use A2G_TC387_3V3_TRB.First of all, I use all cores and referred Demo(AscLinAscDemo, CanBasicDemo) source code to develop. 1. ASC... Show More
User17474
AURIX™
Hello *,We are developing a safety-critical application (IEC61508 - SIL2) using both the toolchain and the PXROS-HR operating system provided by Hight... Show More
User20514
AURIX™
Hello,My question is as follows,Is it possible to generate two indepdendant phase shift outputs from channel 1 and channel 2 w.r.t to master output si... Show More
User9635
AURIX™
Hello Support,Shown below the CPU Access Latency Table from Aurix 2G User Manual.Where do I obtain the "Module Wait State" values for each Peripheral ... Show More
nsyed
AURIX™
Can anyone please help with the below question. I believe it is very basic, but I wanted to make sure that I am doing it correctly.In the MCAL evaluat... Show More
User20618
AURIX™
Hello, I'm using "TC277TP" Aurix controller with 20M Hz external oscillator. Now i want to remove external load capacitances of oscillator and use int... Show More
User20429
AURIX™
Hi,I got a trouble with an TC275 chip when flashing new firmware by memtool with editing BMHD at address 0x80000000.After that, I cannot connect to th... Show More
User16855
AURIX™
HiRecently I got in troubles by trying to use safety watchdog in combination with SMU on TC222The problem is that when trying to initialize safety wat... Show More
User14659
AURIX™
Hello All,I am facing problem with respect to JTAG while trying to connect using UDE debugger. Error says JTAG Interface is locked. This microcontroll... Show More
Forum Information

AURIX™

In this forum you can post your questions, comments and feedback about the 32-bit AURIX™ TriCore™ Microcontroller. The AURIX™ offers the highest scalability in performance, memory & peripherals across application. It is a safe and secure companion chip, meeting both the ISO functional safety standards and EVITA full security standards. Here you can also find the links to the latest board pages, SW and Tools GitHub, trainings, documents and FAQs