AURIX™ Forum Discussions
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AURIX™
Question interrrupt
Solved
Hello,I am trying to disable interrupt by using compile attribute(__disable() amd __enable()).Do these work for all cores, or only the current core ?K...
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Hello,
I am trying to disable interrupt by using compile attribute(__disable() amd __enable()).
Do these work for all cores, or only the current core ?
Kind regards,
Senga Show Less
I am trying to disable interrupt by using compile attribute(__disable() amd __enable()).
Do these work for all cores, or only the current core ?
Kind regards,
Senga Show Less
AURIX™
Hello,do you have any Flash/EEPROM endurance calculator for Aurix 2G TC367? If yes, could please share it?Renesas has a excel sheet called EEPROM Emul...
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Hello,
do you have any Flash/EEPROM endurance calculator for Aurix 2G TC367? If yes, could please share it?
Renesas has a excel sheet called EEPROM Emulation Endurance Calculation Sheet and NXP has an application for that.
https://renesasrulz.com/rh850/f/rh850-forum/17468/rh850-f1k-flash-endurance-calculator
https://community.nxp.com/t5/S32K/Flex-Memory-Endurance-calculator/m-p/1224825
Thanks in advance,
Hakan Show Less
do you have any Flash/EEPROM endurance calculator for Aurix 2G TC367? If yes, could please share it?
Renesas has a excel sheet called EEPROM Emulation Endurance Calculation Sheet and NXP has an application for that.
https://renesasrulz.com/rh850/f/rh850-forum/17468/rh850-f1k-flash-endurance-calculator
https://community.nxp.com/t5/S32K/Flex-Memory-Endurance-calculator/m-p/1224825
Thanks in advance,
Hakan Show Less
AURIX™
Hello, Can I configure Application/System Reset to re-initialize/clear DSPRs/PSPRs ?I have selected following configuration, however DSPRs/PSPRs are n...
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Hello,
Can I configure Application/System Reset to re-initialize/clear DSPRs/PSPRs ?
I have selected following configuration, however DSPRs/PSPRs are not getting cleared when I command application reset via using IfxScuRcu_performReset iLLD API.
- DMU_HF_PROCONRAM.RAMIN = 0 (Init_All, RAM initialization is performed after cold power-on- reset and warm power-on-reset.)
- DMU_HF_PROCONRAM.RAMINSEL = 0 (RAMs (PSPR, DSPR, PCACHE and DCACHE) in CPU0, CPU1 & CPU2 are selected for initialization)
Any thoughts ? Show Less
Can I configure Application/System Reset to re-initialize/clear DSPRs/PSPRs ?
I have selected following configuration, however DSPRs/PSPRs are not getting cleared when I command application reset via using IfxScuRcu_performReset iLLD API.
- DMU_HF_PROCONRAM.RAMIN = 0 (Init_All, RAM initialization is performed after cold power-on- reset and warm power-on-reset.)
- DMU_HF_PROCONRAM.RAMINSEL = 0 (RAMs (PSPR, DSPR, PCACHE and DCACHE) in CPU0, CPU1 & CPU2 are selected for initialization)
Any thoughts ? Show Less
AURIX™
Hi there,
Core 1 on TC27x is a 1.6P. Can I push the cpu frequency to 300MHz?
Thanks,
Ke
Core 1 on TC27x is a 1.6P. Can I push the cpu frequency to 300MHz?
Thanks,
Ke
AURIX™
Some software functionality that is safety-critical should be executed by a lock-stepped processor in a TC27x microcontroller.In the TC27x, there are ...
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Some software functionality that is safety-critical should be executed by a lock-stepped processor in a TC27x microcontroller.
- In the TC27x, there are two processors with checker cores, TC1.6P and TC1.6.E. I am wondering, what would be the procs/cons of choosing either of the two for such executions?
- During start-up after a cold-reset, if only CPU0's lock-stepped mode is enabled, does this interfere with the initialization sequence shown in the attachment (copied from ap32201_TC2xx_StartupAndInitialization.pdf) ?
- During start-up after a cold-reset, if only CPU1's lock-stepped mode is enabled, does this interfere with the initialization sequence shown in the attachment(copied from ap32201_TC2xx_StartupAndInitialization.pdf) ?
- During start-up after a cold-reset, if both CPU0 and CPU1's lock-stepped modes are enabled, how might the initialization sequence look like?
AURIX™
We are using Taskings compiler for a project with Aurix TC33I don’t know how to manage interrupt vector placement in the file: Lcf_Tasking_Tricore_Tc3...
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We are using Taskings compiler for a project with Aurix TC33
I don’t know how to manage interrupt vector placement in the file: Lcf_Tasking_Tricore_Tc33.lsl
The vectors are places on expected addresses but there seems to be code in between:
a. Vectors that are back-to-back of each other
b. On addresses with unused vectors
I would have expected an area with only “vector”-code
1. What would happen if a previous boot-application have left an interrupt active and the trailing customer-application does not have that vector defined?
2. How do I keep other application code out of my vector-area?
// Lcf_Tasking_Tricore_Tc33.lsl
…
#define LCF_INTVEC0_START 0x80001000
…
#define INTTAB0 (LCF_INTVEC0_START)
…
/*Fixed memory Allocations for Interrupt Vector Table*/
group (ordered)
{
group int_tab_tc0 (ordered)
{
#include "inttab0.lsl"
}
"_lc_u_int_tab" = (LCF_INTVEC0_START);
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
} Show Less
I don’t know how to manage interrupt vector placement in the file: Lcf_Tasking_Tricore_Tc33.lsl
The vectors are places on expected addresses but there seems to be code in between:
a. Vectors that are back-to-back of each other
b. On addresses with unused vectors
I would have expected an area with only “vector”-code
1. What would happen if a previous boot-application have left an interrupt active and the trailing customer-application does not have that vector defined?
2. How do I keep other application code out of my vector-area?
// Lcf_Tasking_Tricore_Tc33.lsl
…
#define LCF_INTVEC0_START 0x80001000
…
#define INTTAB0 (LCF_INTVEC0_START)
…
/*Fixed memory Allocations for Interrupt Vector Table*/
group (ordered)
{
group int_tab_tc0 (ordered)
{
#include "inttab0.lsl"
}
"_lc_u_int_tab" = (LCF_INTVEC0_START);
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
} Show Less
AURIX™
board: TC397_TFT_5VI tried to modify the information of UCB_OTP0_ORIG, after which Memtool could not connect to TC397, and the ESR0 light. Check the ...
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board: TC397_TFT_5V
I tried to modify the information of UCB_OTP0_ORIG, after which Memtool could not connect to TC397, and the ESR0 light.
Check the User Manual and see that each UCB has an CONFIRMATION.
I made sure that the CONFIRMATION was written incorrectly and it is my understanding that new information should be loaded from UCN_OTP0_COPY, but unfortunately I cannot use memtool to connect to TC397 right now.
How can I solve this problem?
Thank you very much!
helloworldyaya Show Less
I tried to modify the information of UCB_OTP0_ORIG, after which Memtool could not connect to TC397, and the ESR0 light.
Check the User Manual and see that each UCB has an CONFIRMATION.
I made sure that the CONFIRMATION was written incorrectly and it is my understanding that new information should be loaded from UCN_OTP0_COPY, but unfortunately I cannot use memtool to connect to TC397 right now.
How can I solve this problem?
Thank you very much!
helloworldyaya Show Less
AURIX™
HelloI need a TSIM manual,I want to run my progarmme on the TSIM simulator, but I do not know how I can use it.I use the Free Entry Toolchain and in t...
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Hello
I need a TSIM manual,
I want to run my progarmme on the TSIM simulator, but I do not know how I can use it.
I use the Free Entry Toolchain and in the debugger Starterkit I have not found TSIM support.
please there is someone who can help me Show Less
I need a TSIM manual,
I want to run my progarmme on the TSIM simulator, but I do not know how I can use it.
I use the Free Entry Toolchain and in the debugger Starterkit I have not found TSIM support.
please there is someone who can help me Show Less
AURIX™
What is the use case of HSCT controlled, could you please provide an example ?
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AURIX™
In this forum you can post your questions, comments and feedback about the 32-bit AURIX™ TriCore™ Microcontroller. The AURIX™ offers the highest scalability in performance, memory & peripherals across application. It is a safe and secure companion chip, meeting both the ISO functional safety standards and EVITA full security standards. Here you can also find the links to the latest board pages, SW and Tools GitHub, trainings, documents and FAQs
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