AURIX™ Forum Discussions

Hi~

I use the defalut PSI5S example (iLLD_1_0_1_11_0__TC3xx_Demos)to send data.However, data cannot be written to the data register SDRx,The TX port always sends data from the TBUF. I did not fill in the data in the TBUF, why is it automatically changed according to the channel id.

Try to change the SDRx register value, but the write doesn't work,even if the channel isn't enabled(GCR.CENx = 0)

So I would like to ask what is the possible reason, thank you.

Hi i have a question as following :

if i assign the DATA ,bss ,stack into LMU2(0X900C000-0X900FFFFF)  for the variable of CORE2, then using core2 to operation this variable . i wonder if it will lead to the CPU2 load higher than assign this variables to the DSPR(0X50000000-0X50017FFF) in CORE2.  because i think core2 access the LMU2 will cost more time and resource than access the DSPR in CORE2 directly.

waiting for your feedback 

Drar Infineon Expert，

We're using the tc387 EDSADC for resolver application,and we learned some important information from AP32554.

My question is how to design the timing of the software to realize the updating of the sampling results(by service request or

polling, and how to use the sampling results), and the implementation of the SDCAP delay compensation function.

Is it possible to provide some demo of the software design?

Thank you!

Hi all,

I am working on TC212 controller from Infineon and i  have a UDS bootloader and my main application. As per my understanding if we write the 0x23456789 to Bootsignature variable (ram retention done) and reboot the device then device should remain in boot mode until we reset it or flash new hex file to it.

I was able to to flash the bootloader binary file and flash new app image through UDS flasher utility. Now it want to switch from main application to bootloader on certain event  and stay in bootloader to flash new app image .So what i did is, on desired event i updated the Bootsignature to 0x23456789 and reset the board. But it looks like my device is always jumping to main application after reset.

Is my understanding correct?

Is it possible to achieve what i want?

Can anyone explain what could be the reason behind device jumping back to main app?

Is there any detailed documentation for same?

I am attaching my linker files for reference.

1)bootloader.lsl

/**********************************************************************************************************************
 * \file Lcf_Tasking_Tricore_Tc.lsl
 * \brief Linker command file for Tasking compiler.
 * \copyright Copyright (C) Infineon Technologies AG 2019
 * 
 * Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of 
 * business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
 * are agreed, use of this file is subject to following:
 * 
 * Boost Software License - Version 1.0 - August 17th, 2003
 * 
 * Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and 
 * accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
 * and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
 * Software is furnished to do so, all subject to the following:
 * 
 * The copyright notices in the Software and this entire statement, including the above license grant, this restriction
 * and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all 
 * derivative works of the Software, unless such copies or derivative works are solely in the form of 
 * machine-executable object code generated by a source language processor.
 * 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE 
 * COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN 
 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 
 * IN THE SOFTWARE.
 *********************************************************************************************************************/
 
#define LCF_CSA0_SIZE       8k
#define LCF_USTACK0_SIZE    2k
#define LCF_ISTACK0_SIZE    1k

#define LCF_HEAP_SIZE       2k

#define LCF_CPU0            0

#define LCF_DEFAULT_HOST    LCF_CPU0

#define LCF_DSPR0_START     0x70000000
#define LCF_DSPR0_SIZE      48k

#define LCF_CSA0_OFFSET     (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
#define LCF_ISTACK0_OFFSET  (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
#define LCF_USTACK0_OFFSET  (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)

#define LCF_HEAP0_OFFSET    (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)

#define LCF_INTVEC0_START   0xa0010000
#define LCF_TRAPVEC0_START  (0xa0010000 + 0x2000)

#define INTTAB0             (LCF_INTVEC0_START)
#define TRAPTAB0            (LCF_TRAPVEC0_START)

#define RESET               0xa0000020

#include "tc1v1_6_x.lsl"

// Specify a multi-core processor environment (mpe)

processor mpe
{
    derivative = tc21A;
}

derivative tc21A
{
    core tc0
    {
        architecture = TC1V1.6.X;
        space_id_offset = 100;          // add 100 to all space IDs in the architecture definition
        copytable_space = vtc:linear;   // use the copy table in the virtual core for 'bss' and initialized data sections
    }
    
    core vtc
    {
        architecture = TC1V1.6.X;
        import tc0;                     // add all address spaces of core tc0 to core vtc for linking and locating
    }
    
        bus sri
        {
                mau = 8;
                width = 32;

                // map shared addresses one-to-one to real cores and virtual core, segments starting from 0x0
                map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0x10000000);
                map (dest=bus:tc0:fpi_bus, src_offset=0x10000000, dest_offset=0x10000000, size=0x10000000);
                map (dest=bus:tc0:fpi_bus, src_offset=0x20000000, dest_offset=0x20000000, size=0x10000000);
                map (dest=bus:tc0:fpi_bus, src_offset=0x30000000, dest_offset=0x30000000, size=0x40000000);
                map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0x10000000);
                map (dest=bus:vtc:fpi_bus, src_offset=0x10000000, dest_offset=0x10000000, size=0x10000000);
                map (dest=bus:vtc:fpi_bus, src_offset=0x20000000, dest_offset=0x20000000, size=0x10000000);
                map (dest=bus:vtc:fpi_bus, src_offset=0x30000000, dest_offset=0x30000000, size=0x40000000);

                // map shared addresses one-to-one to real cores and virtual core, segments starting from 0x8
                map (dest=bus:tc0:fpi_bus, src_offset=0x80000000, dest_offset=0x80000000, size=0x40000000);
                map (dest=bus:vtc:fpi_bus, src_offset=0x80000000, dest_offset=0x80000000, size=0x40000000);

                // map shared addresses one-to-one to real cores and virtual core, segments starting from 0xe
                map (dest=bus:tc0:fpi_bus, src_offset=0xe0000000, dest_offset=0xe0000000, size=0x20000000);
                map (dest=bus:vtc:fpi_bus, src_offset=0xe0000000, dest_offset=0xe0000000, size=0x20000000);
                
                // map local memory
                map (dest=bus:tc0:fpi_bus, src_offset=0x70000000, dest_offset=0x70000000, size=0x00100000, priority=2, exec_priority=0);
                map (dest=bus:tc0:fpi_bus, src_offset=0x70100000, dest_offset=0x70100000, size=0xff00000, exec_priority=2);
                map (dest=bus:vtc:fpi_bus, src_offset=0x70000000, dest_offset=0x70000000, size=0x10000000);
        }
    
    memory dsram0 // Data Scratch Pad Ram
    {
        mau = 8;
        size = 48k;
        type = ram;
        map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=48k, priority=8);
        map (dest=bus:sri, dest_offset=0x70000000, size=48k);
    }
    
    memory psram0 // Program Scratch Pad Ram
    {
        mau = 8;
        size = 8k;
        type = ram;
        map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=8k, priority=8);
        map (dest=bus:sri, dest_offset=0x70100000, size=8k);
    }
    
    memory pfls0
    {
        mau = 8;
        size = 512k;
        type = rom;
        map     cached (dest=bus:sri, dest_offset=0x80000000,           size=512k);
        map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=512k);
    }
    
    memory dfls0
    {
        mau = 8;
        size = 1M;
        type = reserved nvram;
        map (dest=bus:sri, dest_offset=0xaf000000, size=1M  );
    }

#if (__VERSION__ >= 6003)
    section_setup :vtc:linear
    {
        heap "heap" (min_size = (1k), fixed, align = 8);
    }    
#endif
    
    section_setup :vtc:linear
    {
        start_address
        (
            symbol = "_START"
        );
    }
    
    section_setup :vtc:linear
    {
        stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
        stack "istack_tc0" (min_size = 1k, fixed, align = 8);
    }
    
    /*Section setup for the copy table*/
    section_setup :vtc:linear
    {
        copytable
        (
            align = 4,
            dest = linear,
            table
            {
                symbol = "_lc_ub_table_tc0";
                space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
            }
        );
    }
    
    /*Near data sections*/
    section_layout :vtc:abs18
    {   
        group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
        {
            select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
            select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
        }
#       if LCF_DEFAULT_HOST == LCF_CPU0
        group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
#       endif
        {
            select "(.zdata|.zdata*)";
            select "(.zbss|.zbss*)";
        }
    }

    section_layout :vtc:linear 
    {
/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
#       if LCF_DEFAULT_HOST == LCF_CPU0
        group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
#       endif
        {
            select "(.sdata |.sdata*)";
            select "(.sbss |.sbss*)";
        }
        "_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;

        /*Far data sections*/
        group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
        {
            select "(.data.data_cpu0|.data.data_cpu0*)";
            select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
        }

#       if LCF_DEFAULT_HOST == LCF_CPU0
        group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
#       endif
        {
            select "(.data|.data*)";
            select "(.bss|.bss*)";
        }

/*Heap sections*/
#       if LCF_DEFAULT_HOST == LCF_CPU0
        group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
#       endif
        {
            heap "heap" (size = LCF_HEAP_SIZE);
        }
    
        group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
        {
            stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
        }
        "__USTACK0":=   "_lc_ue_ustack_tc0";
        "__USTACK0_END":=   "_lc_ub_ustack_tc0";
            
        group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
        {
            stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
        }
        "__ISTACK0":=   "_lc_ue_istack_tc0";
        "__ISTACK0_END":=   "_lc_ub_istack_tc0";
        
        group  (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET]) 
            reserved "csa_tc0" (size = LCF_CSA0_SIZE);
        "__CSA0":=      "_lc_ub_csa_tc0";
        "__CSA0_END":=  "_lc_ue_csa_tc0";
    }
    
    
    section_layout :vtc:linear
    {
        "_lc_u_int_tab" = (LCF_INTVEC0_START);
        "__INTTAB_CPU0" = (LCF_INTVEC0_START);
        
        // interrupt vector tables for tc0, tc1, tc2 
        group int_tab_tc0 (ordered)
        {
#           include "inttab0.lsl"
        }
        
        group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
        {
            select "(.text.traptab_cpu0*)";
        }
        
        group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
        {
            select "(.text.psram_cpu0*)";
            select "(.text.cpu0_psram*)";
        }
    }
    
    section_layout :vtc:abs18
    {
        group  (ordered, run_addr=mem:pfls0[11000])
        {
            select ".zrodata*";
        }
    }
    
    section_layout :vtc:linear
    {       
        group  bmh_0 (ordered, run_addr=0x80000000)
        {
            select "*.bmhd_0";
        }
        group  bmh_1 (ordered, run_addr=0x80013000)
        {
            select "*.bmhd_1";
        }
        group  reset (ordered, run_addr=0x80000020)
        {
            select "*.start";
        }
        group  interface_const (ordered, run_addr=0x80000040)
        {
            select "*.interface_const";
        }
        "__IF_CONST" := addressof(group:ainterface_const);
        group  a1 (ordered, run_addr=mem:pfls0[0xF000])
        {
            select ".srodata*";
            select ".ldata*";
        }
        "_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
        "_A1_MEM" = "_LITERAL_DATA_";
        "_A9_DATA_" := 0x00000000;
        "_A9_MEM" = "_A9_DATA_";
        
        group  (ordered, run_addr=mem:pfls0[0xD000])
        {
            select ".rodata*";
        }
        group  (ordered, run_addr=mem:pfls0[0x4020])
        {
            select ".text*";
        }
        group a8 (ordered, run_addr=mem:pfls0[0x10000])
        {
            select "(.rodata_a8|.rodata_a8*)";
        }
        "_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
        "_A8_MEM" := "_A8_DATA_";

        "__TRAPTAB_CPU0" := TRAPTAB0;
    }
	
	
	section_layout :vtc:linear
		{
			group(ordered, run_addr = mem:dsram0[0xBE00])
			{
				section "RESET_SAFE__ECU" (size= 0xFF,attributes = rw)
				{
					select ".bss.DiagManager.BootSignature";
				}		
			}
			
			group(ordered, run_addr = mem:dsram0[0xBF00])
			{
				
				section "RESET_SAFE__BTDLR" (size= 0xFF,attributes = rw)
				{
					select ".bss.SystemInfo.InfoBoot";

				}		
			}
											
		}
}

2)main app.lsl

/**********************************************************************************************************************
 * \file Lcf_Tasking_Tricore_Tc.lsl
 * \brief Linker command file for Tasking compiler.
 * \copyright Copyright (C) Infineon Technologies AG 2019
 * 
 * Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of 
 * business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
 * are agreed, use of this file is subject to following:
 * 
 * Boost Software License - Version 1.0 - August 17th, 2003
 * 
 * Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and 
 * accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
 * and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
 * Software is furnished to do so, all subject to the following:
 * 
 * The copyright notices in the Software and this entire statement, including the above license grant, this restriction
 * and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all 
 * derivative works of the Software, unless such copies or derivative works are solely in the form of 
 * machine-executable object code generated by a source language processor.
 * 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE 
 * COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN 
 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 
 * IN THE SOFTWARE.
 *********************************************************************************************************************/
 
#define LCF_CSA0_SIZE       8k
#define LCF_USTACK0_SIZE    2k
#define LCF_ISTACK0_SIZE    1k

#define LCF_HEAP_SIZE       2k

#define LCF_CPU0            0

#define LCF_DEFAULT_HOST    LCF_CPU0

#define LCF_DSPR0_START     0x70000000
#define LCF_DSPR0_SIZE      48k

#define LCF_CSA0_OFFSET     (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
#define LCF_ISTACK0_OFFSET  (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
#define LCF_USTACK0_OFFSET  (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)

#define LCF_HEAP0_OFFSET    (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)

#define LCF_INTVEC0_START   0x80020000
#define LCF_TRAPVEC0_START  0x80022000

#define INTTAB0             (LCF_INTVEC0_START)
#define TRAPTAB0            (LCF_TRAPVEC0_START)

#define APP_HEADER          0x80018000
#define RESET               0x80018020

#include "tc1v1_6_x.lsl"

// Specify a multi-core processor environment (mpe)

processor mpe
{
    derivative = tc21A;
}

derivative tc21A
{
    core tc0
    {
        architecture = TC1V1.6.X;
        space_id_offset = 100;          // add 100 to all space IDs in the architecture definition
        copytable_space = vtc:linear;   // use the copy table in the virtual core for 'bss' and initialized data sections
    }
    
    core vtc
    {
        architecture = TC1V1.6.X;
        import tc0;                     // add all address spaces of core tc0 to core vtc for linking and locating
    }
    
    bus sri
    {
        mau = 8;
        width = 32;
        
        // map shared addresses one-to-one to real cores and virtual cores
        map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
        map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
    }
    
    memory dsram0 // Data Scratch Pad Ram
    {
        mau = 8;
        size = 48k;
        type = ram;
        map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=48k, priority=8);
        map (dest=bus:sri, dest_offset=0x70000000, size=48k);
    }
    
    memory psram0 // Program Scratch Pad Ram
    {
        mau = 8;
        size = 8k;
        type = ram;
        map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=8k, priority=8);
        map (dest=bus:sri, dest_offset=0x70100000, size=8k);
    }
    
    memory pfls0
    {
        mau = 8;
        size = 416k;
        type = rom;
        map     cached (dest=bus:sri, dest_offset=0x80018000,           size=416k);
        map not_cached (dest=bus:sri, dest_offset=0xa0018000, reserved, size=416k);
    }
    
    memory dfls0
    {
        mau = 8;
        size = 1M;
        type = reserved nvram;
        map (dest=bus:sri, dest_offset=0xaf000000, size=1M  );
    }

#if (__VERSION__ >= 6003)
    section_setup :vtc:linear
    {
        heap "heap" (min_size = (1k), fixed, align = 8);
    }    
#endif
    
    section_setup :vtc:linear
    {
        start_address
        (
            symbol = "_START"
        );
    }
    
    section_setup :vtc:linear
    {
        stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
        stack "istack_tc0" (min_size = 1k, fixed, align = 8);
    }
    
    /*Section setup for the copy table*/
    section_setup :vtc:linear
    {
        copytable
        (
            align = 4,
            dest = linear,
            table
            {
                symbol = "_lc_ub_table_tc0";
                space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
            }
        );
    }
    
    /*Near data sections*/
    section_layout :vtc:abs18
    {   
        group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
        {
            select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
            select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
        }
#       if LCF_DEFAULT_HOST == LCF_CPU0
        group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
#       endif
        {
            select "(.zdata|.zdata*)";
            select "(.zbss|.zbss*)";
        }
    }

    section_layout :vtc:linear 
    {
/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
#       if LCF_DEFAULT_HOST == LCF_CPU0
        group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
#       endif
        {
            select "(.sdata |.sdata*)";
            select "(.sbss |.sbss*)";
        }
        "_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;

        /*Far data sections*/
        group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
        {
            select "(.data.data_cpu0|.data.data_cpu0*)";
            select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
        }

#       if LCF_DEFAULT_HOST == LCF_CPU0
        group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
#       endif
        {
            select "(.data|.data*)";
            select "(.bss|.bss*)";
        }

/*Heap sections*/
#       if LCF_DEFAULT_HOST == LCF_CPU0
        group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
#       endif
        {
            heap "heap" (size = LCF_HEAP_SIZE);
        }
    
        group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
        {
            stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
        }
        "__USTACK0":=   "_lc_ue_ustack_tc0";
        "__USTACK0_END":=   "_lc_ub_ustack_tc0";
            
        group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
        {
            stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
        }
        "__ISTACK0":=   "_lc_ue_istack_tc0";
        "__ISTACK0_END":=   "_lc_ub_istack_tc0";
        
        group  (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET]) 
            reserved "csa_tc0" (size = LCF_CSA0_SIZE);
        "__CSA0":=      "_lc_ub_csa_tc0";
        "__CSA0_END":=  "_lc_ue_csa_tc0";
    }
    
    
    section_layout :vtc:linear
    {
        "_lc_u_int_tab" = (LCF_INTVEC0_START);
        "__INTTAB_CPU0" = (LCF_INTVEC0_START);
        
        // interrupt vector tables for tc0, tc1, tc2 
        group int_tab_tc0 (ordered)
        {
#           include "inttab0.lsl"
        }
        
        group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
        {
            select "(.text.traptab_cpu0*)";
        }
        
        group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
        {
            select "(.text.psram_cpu0*)";
            select "(.text.cpu0_psram*)";
        }
    }
    
    section_layout :vtc:abs18
    {
        group  (ordered, run_addr=mem:pfls0[0xC000])
        {
            select ".zrodata*";
            select ".zdata*";                   
        }
    }
    
    section_layout :vtc:linear
    {       
        group  reset (ordered, run_addr=RESET)
        {
            select "*.start";
        }

        group  appHeader (ordered, run_addr=APP_HEADER)
        {
            select ".rodata.Cpu0_Main.SwUnit_header";
            select ".rodata.Cpu0_Main.reserved_sec";
        }

        group  bmh_0 (ordered, run_addr=mem:pfls0[0xE000])
        {
            select "*.bmhd_0";
        }
		
		
		group(ordered, run_addr = mem:dsram0[0xBE00])
        {
            section "RESET_SAFE__ECU" (size= 0xFF,attributes = rw)
            {
                select ".bss.DiagManager.BootSignature";
            }       
        }
    
        
			
		group  bmh_1 (ordered, run_addr=mem:pfls0[0x10000])
		{
			select "*.bmhd_1";
		}
        
        group  interface_const (ordered, run_addr=mem:pfls0[0x12000])
        {
            select "*.interface_const";
        }
        
        "__IF_CONST" := addressof(group:ainterface_const);
        group  a1 (ordered, run_addr=mem:pfls0[0x14000])
        {
            select ".srodata*";
            select ".ldata*";
        }

        "_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
        "_A1_MEM" = "_LITERAL_DATA_";
        "_A9_DATA_" := 0x00000000;
        "_A9_MEM" = "_A9_DATA_";
        
        group  (ordered, run_addr=mem:pfls0[0x16000])
        {
            select ".rodata*";
        }
          
	group a8 (ordered, run_addr=mem:pfls0[0x18000])
	{
		select "(.rodata_a8|.rodata_a8*)";
        }        
	
	group  (ordered, run_addr=mem:pfls0[0x20000])
	{
		select ".text*";
        }
        
        "_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
        "_A8_MEM" := "_A8_DATA_";

        "__TRAPTAB_CPU0" := TRAPTAB0;
    }
}

Hello,

I need to measure run time of a function on TC399. For that, I am making use of GPT12 timer module. 

I have written the following snippet.

initial_value = IfxGpt12_T3_getTimerValue(&MODULE_GPT120);

My_custom_function();

final_value = IfxGpt12_T3_getTimerValue(&MODULE_GPT120);

// Note: I have set the timer direction down.

// Calculate the elapsed timer ticks
if (final_value <= initial_value) {
elapsedTicks = initial_value - final_value ;
} else {
// Timer has wrapped around :: MAX_VALUE=0xFFFF; 
elapsedTicks = (MAX_VALUE - final_value ) + initial_value + 1;
}

uint32 timerFrequency = IfxGpt12_T3_getFrequency(&MODULE_GPT120);
uint32 elapsedMilliseconds = (elapsedTicks * 1000) / timerFrequency;

However, sometimes, the run time value is showed as 0ms. I am sure, there is something going wrong. Can you please help me?

Also, does  'IfxGpt12_T3_getTimerValue' this return ticks? 

Please guide me through the process.
Thanks in advance!

Hello,

I have been playing with the TC299_TRB and, while I am able to run code and store data in the LMU and DSPR, I did not find information on its external RAM (if I understood the documentation, there is one). Which address range is it mapped to?

Thanks!

Best regards,

Ricardo

Hello,

I have to clear RSTSTAT register in TC322LP. Cold PORST and STANDBY related registers can clear with RSTCON2.CLR bit. But how can I clear RSTSTAT.B.SW and others ? RSTSTAT register's access mode for write is Bus Error. If I try to write on this register, it returns bus error. Is there any way to clear this register with different way ?

Thanks for helps.

I would like to know, in the ED stage, what kind of scenes can OLDA as an overlay target memory be used in?

For example, to redirect OLDA to EMEM, you can write the OLDA address directly through the calibration tool, but actually modify the contents of EMEM.