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User21011
Level 1
Level 1
I am working to understand the DMA which has an APB4 slave interface for configuration and a AXI4 master interface for DMA transfer. As AXI4 has axcache, axprot and axqos signals, I want to know that for a valid DMA transfer what will be the appropriate values for these signals considering memory-to-memory, memory-to-peripheral, peripheral-to-memory and peripheral-to-peripheral data transfers?
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