Write to Core Special Function Register

[User22023]

Hello all,

i´ve tried to write from Core 1 to the CSFR´s from Core 0 and Core 1 directly by using pointers to the register. No MFCR and MTCR Instructions!
The Register are the Codeprotectionrange0 (upper bound) of core 0 and 1, and the PSW of both Cores.
Now i´m confused because if i write from core 1 to csfr`s of core 0 it works and i can see the values in the register view in the debugger.
But if i trie to write to the own CSFR´s(core 1) or if i do all this stuff from core 0 i got an instruction error with Trap ID 5.

Can someone please explain me what´s goin on here and why do i need the mfcr and mtcr instructions.

Aurix TC387

Thanks & BR Hennessy

[NeMa_4793301 · Accepted solution]

Think of MTCR as a kind of protection, similar to ENDINIT and Safety ENDINIT. Having a master CPU set up the other CPUs is allowed, by writing to the other core CSFRs via the SRI bus. Having a CPU write to its own CSFRs via the SRI bus is not allowed.

From TriCore_TC162P_core_architecture_volume_1_of_2.pdf:

Implementation constraints which can raise the MEM trap are
• A memory address is used to access a Core SFR (CSFR) rather than using a MTCR/MFCR instruction (CSFR access)

[User22023]

Ok i understand, thank you again for the great answer.