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AURIX™ Forum Discussions

User17612
Level 3
Level 3
First like received
Hi all,

Will traps be generated when calculating FPU operation and zero division occurs?

Kind regards,
Lucas

#8042000 13380
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3 Replies
User18237
Level 5
Level 5
First solution authored First like received
Hi Lucas,

This could be enabled if the trap enable flag in the FPU_TRAP_CON register is set for the corresponding event. (In this case a FZ Divide by Zero event, but note that in the case for 0/0, an FI is asserted rather than an FZ.)
The reset value is “disable” for the generation of a trap. The generated trap would be a Co-Processor Asynchronous error. Please check the architecture manual for further details.

Best regards,
Mr. AURIX™
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User13836
Level 5
Level 5
10 solutions authored 50 replies posted 25 sign-ins
Hello Lucas,

in addition to the FP trap support provided by the AURIX CPU hardware the compiler also allows to implement floating point trapping via software. This is configured in menu:

TASKING C Compiler >> Floating-point

for the AURIX Development Studio and

C/C++ Compiler >> Floating-point

for the commercial TASKING TriCore toolset.

-> Option: support trapping on exceptions

Using this it's possible to implement a self defined trap handler for the various FP traps sources.

Best regards,
Ulrich Kloidt

TASKING tools support
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User13836
Level 5
Level 5
10 solutions authored 50 replies posted 25 sign-ins
I need to update my statement. The AURIX Development Studio does not support using different FP settings. Although the menu doea allow this the options are not passed to the C compiler / linker. So for the AURIX Development Studio only single precision FP with hardware FPU support and no software FP trapping seems to be supported. For the commercial TASKING TriCore tools this is fully configurable instead. I'm sorry for the confusion.

Best regards,
Ulrich Kloidt
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