It is something of new for me. All the other uC I've used do not have this limitation. I've done a look on the iLLD and this "robust" eeprom emulation methods seems not covered.
So I suppose it is all demanded to the application engineer to add this algorithm. There are some indication or example ?
what is the "involved" area of this problem. If I erase one sector (4kbyte) of DFLASH0_EEPROM I've to re-write the whole DFLASH0_EEPROM or the whole DFLASH0 included the UCBs?
Another question: the user manual report
"Before programming a page save the content of all other pages on the same wordline that contain active data
What is a wordline in this Dflash architecture? where I can find the relative references?
Hoping someone from IFX will reply.....
Checking on MY ICP there is a presentation related to TC2 about the FEE/FLS. Here is reported that the maximum number of block (n) has to be choosen considering the Erase disturb with the following criteria n-1 < 50
But as far as I've understood the FEE perform at least 2 clear action (for example erase->used->full) to update during the sector life the status, so it should be something like 2n-1<50. Is my assumption correct?
For your original question:
If I erase one sector (4kbyte) of DFLASH0_EEPROM I've to re-write the whole DFLASH0_EEPROM or the whole DFLASH0 included the UCBs?
Think of the erase disturb as spray painting on a windy day: each erase operation erases the intended sector, but can degrade other parts of data flash. Each erase operation counts against the erase disturb limit; erasing multiple sectors in a single operation counts as one disturb.
For wordlines, see "Flash Structure Terms" in the User Manual part 1: for DFLASH, wordlines are 512 bytes.
The Infineon MCAL FEE divides DFLASH into two logical sectors; when one side is full, it erases the other side, and then copies the latest instance of each data item to the freshly erased side. That method counts as a single disturb, because only one erase operation is performed.
thanks for the feedback and for the description of what MCAL do.
About the worldline it is still not so clear what is exactly, probably the architecture of the memory is different of what I've in my mind (simply 2d matrix wordline/bitline ). In the manual is marked that the world lines is 512 bytes so probably it is referring to something different.
In any case: When I do a clear I can act on a sector (in this uC the sector is 4k -> 8 wordline? ). The manual report that we need to "Before programming a page save the content of all other pages on the same wordline that contain active data to SRAM."
What does it meand the "other pages on the same wordline"?
Hi FD_aurix. Data flash pages are 8 bytes, while data flash wordlines are 512 bytes. If a wordline fails, it can corrupt or freeze all 512 bytes. As a worst case example, an application may have recorded 504 bytes in a wordline successfully, and then encounter a wordline failure while programming the last page of 8 bytes - losing the whole wordline. A driver that holds the wordline in memory can recover from this kind of failure by rewriting the data to the next wordline.
ok, so we are talking about the other pages on the same wordline where with consecutive addresses.
So we can sum up in the following way
DFLASH is divided in pages, wordline and sector
Each page is 8 bytes
Each wordline is 512 bytes-> 64 pages
Each sector is 4096 bytes->512 pages ->8 wordline
Sector, wordline and pages are address aligned