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Level 3
Level 3
First like received 10 replies posted 25 sign-ins

Dear all,

In document "AP32381_AURIX_2ndGeneration_Startup_and_Initialisation_V1.2.pdf", (see attachment INTTAB.png)

it describes that each SRPN is occupied 8 or 32 bytes.

From my understanding, INT address is 32bit size or 4bytes,

Why and what are these 8 bytes or 32bytes?

 

 

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cwunder
Employee
Employee
10 likes given 100 solutions authored 5 likes given

See this section in the user's manual

16.11.1 Use Case Example Interrupt Handler
By using the 32 Byte configuration small interrupt routines can the implemented directly into the vector table.
They can even span multiple vector entries (see the TriCore Architecture Manual). This type of fast interrupt
handling is useful, if the vector table can be located into the TriCore program side memory. The 8 Byte
configuration reduces the vector table size. Each vector entry contains only a jump instruction or a call and return
as 16-bit op-code instruction. The TriCore compiler supports this kind of interrupt vector table generation by
keywords or functions. A minimum vector table can be configured if the BIV mask the PIPN so that any interrupt
address calculation results in the same address.

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cwunder
Employee
Employee
10 likes given 100 solutions authored 5 likes given

See this section in the user's manual

16.11.1 Use Case Example Interrupt Handler
By using the 32 Byte configuration small interrupt routines can the implemented directly into the vector table.
They can even span multiple vector entries (see the TriCore Architecture Manual). This type of fast interrupt
handling is useful, if the vector table can be located into the TriCore program side memory. The 8 Byte
configuration reduces the vector table size. Each vector entry contains only a jump instruction or a call and return
as 16-bit op-code instruction. The TriCore compiler supports this kind of interrupt vector table generation by
keywords or functions. A minimum vector table can be configured if the BIV mask the PIPN so that any interrupt
address calculation results in the same address.

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Level 3
Level 3
First like received 10 replies posted 25 sign-ins

Hi Cwunder,

To sum up from my current understanding is

32 byte configuration : the ISR are directly into the vector table for fast interrupt handling. (thing to do inside ISR should be as sample as possible, though the can span multiple vector entries)

8 byte configuration : reduce vector table size but ISR speed is slower than 32 byte configuration

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cwunder
Employee
Employee
10 likes given 100 solutions authored 5 likes given

No, the point is you don't need all 32 bytes to create a simple jump table in the vector table. The default for both configurations is to jump to another location in code for the ISR execution (so the speed is the same). You can span multiple interrupt entries with both. Just that you will span more with the 8 byte configuration so if you want to do this then the 32 byte is more applicable.  The 8 byte configuration is generally used when you locate the vector table in RAM to save space.

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