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yrun431
Level 2
Level 2
10 replies posted 10 sign-ins 5 replies posted

Hi,

I am using Tc37x.

I want my SMU to track MTU alarms all the time. For that I have written the code something like this

  IfxMtu_enableModule();
clear_MTU_MBIST_Errors(IfxMtu_MbistSel mbistSel);
 
Basically, just enabled the MTU clock and then clear the errors caused due to system reset.
Now which other functions should I write [ from IfxMtu.h] to continuosly track the MTU errors.
 
 
I have a few questions:
1] for DAM0 do I need to enable DAM0 module too? [by enabling DAM0_CLC?]
2] If I get any MTU error, will my corresponding smu alarms get set automatically? [ As i need to check if smu alarms are set or not, does it happen auto? or do i have to set "AlarmStatus" after configuring MTU bits?]
3] I can see that FSI_RAM is not used in the enum. So do how should I disable this alarm after system reset?
 
4] I want to set an alarm status in smu (say alm0[9-11]) and lets say I choose  mbistSel =  IfxMtu_MbistSel_cpu0Dspr.
How to set this MTU alarm ? and the corresponding SMU alarm?
 
5] and for DMA/gigethernet 
yrun431_0-1642750691402.png

 

I cleared the mbist 41[DMA] and 82,83[ethermacRx/Tx]. But the smu alarm doesn't set to "low", its still "high".

 
 
Thank you!!
 
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1 Solution
µC_Wrangler
Employee
Employee
50 solutions authored 100 sign-ins 25 likes received

The PMS registers are easier - no exotic clearing/latches/etc.  But keep in mind that the primary voltage monitors are always active, and you might not need to use the secondary voltage monitoring at all.

View solution in original post

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6 Replies
yrun431
Level 2
Level 2
10 replies posted 10 sign-ins 5 replies posted

@µC_Wrangler 

Can you please help with this

Thanks

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µC_Wrangler
Employee
Employee
50 solutions authored 100 sign-ins 25 likes received

1) If you're not using DAM, don't worry about testing DAM0.

2) MTU errors will only set the corresponding alarm if ECCS CENE/UCENE/MENE are set.

3) For the TC37x, LMU and FSI alarms are combined, so I don't recommend disabling the alarm.  Write 0 to MC40_ECCD as recommended in application hint SMU_TC.H012 in the Errata Sheet.

4) My general advice is to avoid injecting low-level failures that result in an SMU alarm.  The LBIST tests all of AURIX logic, so there's no need to test the full alarm path for each safety mechanism.  To test your application's reaction to each alarm, leave the SMU in START state, and then you can simply write to SMU_AGx in the debugger.
After you clear MTU error flags, you still need to clear the alarm within the SMU itself.

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thank you @µC_Wrangler 

 

In the 

clear_MTU_MBIST_Errors()
   ->  IfxMtu_clearErrorTracking(mbistSel);                    /* Clear the error tracking registers (ETRR)    */
 
function is called. So do i need to enable the error tracking again, so as to always keep checking for the MTU errors?
 
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µC_Wrangler
Employee
Employee
50 solutions authored 100 sign-ins 25 likes received

IfxMtu_clearErrorTracking clears the "alarm occurred" bits in MCi_ECCD.  The alarm enable bits are in MCi_ECCS.  Once the alarm is enabled, you don't need to periodically check for MTU errors, unless you've configured the corresponding SMU alarm reaction to no action.

Thank you @µC_Wrangler 

Can you please tell me,

how to access pms and hsm regs in smu alarm -> alm9[3,5,15,16,17]. Is it similar to MTU, that we need to enable and check mtu and then smu

or directly can we just check smu?

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µC_Wrangler
Employee
Employee
50 solutions authored 100 sign-ins 25 likes received

The PMS registers are easier - no exotic clearing/latches/etc.  But keep in mind that the primary voltage monitors are always active, and you might not need to use the secondary voltage monitoring at all.

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