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StevenAris
Level 1
Level 1
5 sign-ins First reply posted First question asked

I'm running an AURIX TC275 and seeing SRI Protocol Errors triggered by writes to Flash.  The errors do not occur consistently in the same Flash Page and also appear to be independent of what is being written.

I've found references to an SRI Protocol Specification, but cannot find it in myinfineon or anywhere else and the TC275 User Manual does not explain exactly what an SRI Protocol Error is.

Please could someone either point me to some relevant documentation or perhaps provide an explanation of what an SRI Protocol Error is and what is likely to have triggered it.

Best regards,

Steve

 

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µC_Wrangler
Employee
Employee
50 solutions authored 100 sign-ins 25 likes received

Hi Steve.  "Protocol error" is almost always a write to an invalid address.  I'd start with page 112 of tc27xD_um_v2.2.pdf ("non existing addresses" and "Error Handling"), but that's a challenging section of the manual.

What address is the code at that writes to PFLASH?  The AURIX does not support read-while-write,  which means you have to make sure you're not running from the same PFLASH bank that you're writing to.  That restriction includes all operations, such as DMA and interrupts.  Anything that reads from flash while an erase or write is in progress will lead to an SRI error.

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µC_Wrangler
Employee
Employee
50 solutions authored 100 sign-ins 25 likes received

Hi Steve.  "Protocol error" is almost always a write to an invalid address.  I'd start with page 112 of tc27xD_um_v2.2.pdf ("non existing addresses" and "Error Handling"), but that's a challenging section of the manual.

What address is the code at that writes to PFLASH?  The AURIX does not support read-while-write,  which means you have to make sure you're not running from the same PFLASH bank that you're writing to.  That restriction includes all operations, such as DMA and interrupts.  Anything that reads from flash while an erase or write is in progress will lead to an SRI error.

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Thanks for the reply uC_Wrangler, that is useful to know.

In this instance however, the write is to DFLASH (Bank 0) and I don't believe there are any read accesses ongoing at the same time, but I will double-check as it sounds a likely culprit.

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Hi uC_Wrangler,

Thanks for the references in the user manual, although I still can't see any thing that clarifies exactly what an SRI Protocol error is, or what may cause it.

However, to confirm, I have temporarily enabled the FCON.Stall option and the SRI Protocol errors no longer appear to happen, which (although I've so far failed to find it) I think confirms your  assertion that the cause is a read of DFlash while a write is in progress.

Many thanks,

Steve

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µC_Wrangler
Employee
Employee
50 solutions authored 100 sign-ins 25 likes received

Hi Steve.  "Protocol error" is a catch-all: the SRI bus can assert starvation errors, transaction ID errors, and protocol errors.

  • Starvation occurs if higher priority bus masters are hogging the bus
  • Transaction ID errors occur if there's a request to an invalid bus slave number, or from an invalid bus master number
  • Protocol errors are everything else (i.e., access blocked, invalid address, etc.)

Be careful with FCON.STALL - it can lead to all sorts of misadventures.  The most common example of trouble is that watchdogs are enabled, and a multiple sector erase can take up to 1000 ms.  That often leads to a watchdog reset.

Thank uC_Wrangler,

That is nice and clear.

And thanks for the warning about FCON.Stall - I was setting it just to try and confirm whether we were writing and reading the Flash simultaneously, but I will be extra careful to make sure it doesn't get into our product.

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