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AURIX™

User9635
New Contributor
Hello Support,
Shown below is a snippet from TRAPSTAT register Bit 2 .
Can you please tell me what is the source for this TRAP2?
What configuration does set this Bit TRAP2?
Please provide some section number from the User Manual where TRAP2 is described.
4326.attach

Best Regards
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5 Replies
Darren_Galpin
New Contributor
That is set from TRAPSET.TRAP2. Writing 1 to TRAPSET.TRAP2 sets TRAPSTAT.TRAP2 to 1.
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User9635
New Contributor
Hello Support,

So when software triggers TRAPSET.TRAP2, then it is not a CPU Trap generation I suppose.
If not, then which SMU Alarm Signal will be activated?
If it is a CPU Core Trap, then what is Trap Vector Number and what is the expected value of D15 Register [TIN] upon entering CPU Trap Vector.
Best Regards
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Darren_Galpin
New Contributor
I believe that this causes an NMI trap (non-maskable interrupt), so TIN=0, class=7 (so CPU core trap).
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FD_aurix
New Contributor II

Hi all

so this is only activable via SW. Or it might be related to some HW pins as ESR0/ESR1?

 

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MoD
Employee

It is only activatable via SW.

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