May 16, 2020
04:16 AM
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May 16, 2020
04:16 AM
Hello Support,
Please provide me the Instruction Mnemonic for Read-Modify-Write for Aurix 2G as shown below for IR_SRC Register ECC bit-field.

Best Regards
Please provide me the Instruction Mnemonic for Read-Modify-Write for Aurix 2G as shown below for IR_SRC Register ECC bit-field.
Best Regards
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May 16, 2020
06:48 AM
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May 16, 2020
06:48 AM
From Chapter 2 in the User Manual:
Support of atomic CPU operations e.g. LDMST, ST.T, SWAP.W, CMPSWP and SWPMSK
Also see 5.3.4.10 Atomicity of Data Accesses.
Also see TriCore Architecture Manual Volume 1, 2.4 Semaphores and Atomic Operations.
Support of atomic CPU operations e.g. LDMST, ST.T, SWAP.W, CMPSWP and SWPMSK
Also see 5.3.4.10 Atomicity of Data Accesses.
Also see TriCore Architecture Manual Volume 1, 2.4 Semaphores and Atomic Operations.