AURIX™ Forum Discussions

[User18151]

Hi all ,

What is all pin status during standby mode on AURIX™-TC2xx?

Kind regards
Christine

#8042000 12464

[User18237]

Hi Christine,

TC29x/TC27x
GPIOs : PU or Tristate by PMSWCR0.TRISTREQ
ESR0 : Open drain with weak PU or Tristate by PMSWCR0.ESR0TRIST
ESR1 : PU
Pin A/B : PU or Tristate by PMSWCR0.TRISTREQ
PORST Output : Weak PD

TC26x
GPIOs : PU or Tristate by PMSWCR0.TRISTREQ
ESR0 : Open drain with weak PU or Tristate by PMSWCR0.ESR0TRIST
ESR1 : PU
Pin A/B : PU or Tristate by PMSWCR0.TRISTREQ
PORST Output : Weak PD

TC23x/22x/21x
GPIOs : Tristate (except P14.1, P14.3, P14.6 and P21.7 which are with PU)
ESR0 : Open drain with weak PU or Tristate by PMSWCR0.ESR0TRIST
ESR1 : PU
Pin A/B : Tristate
PORST Output : Weak PD

I hope that was the answer you were looking for .

Kind regards
Mr.AURIX™

[User9635]

Hello Support,

Can you please tell me which Pad or Port or BGA Ball you are referring for Pin A/B:?
My device is TC297 BGA-292 package.
You can tell me for any package, that is also fine.
I can map it correspondingly.
Thank you.
Regards

[NeMa_4793301]

PINA is 14.1 (ball A15 on a TC297). It's labeled EVRWUPA in the datasheet, which isn't a very direct link.
PINB is 15.1 (ball A18 on a TC297). EVRWUPB in the datasheet.

[User9635]

Hello Support,

In my hardware design HWCFG[6] is strongly pulled to ground for TC297 device, HWCFG[6]=0.
So, according to TC29x user manual, the port pins are in Tri-State after Cold Power On Reset, till software changes the default pin behavior during run-time.
PMSWCR0.TRISTREQ is kept at default value of zero by software.

During any subsequent run-time Warm Reset/ System Reset / Application Reset of the hardware, will the port pins become Tri-State irrespective of run-time software configuration when PMSWCR0.TRISTREQ=0 is maintained by software?
Or, I must make PMSWCR0.TRISTREQ=1 to go to Tri-State during Warm Reset/ System Reset/ Application of the hardware?
Thank you.
Regards

[cwunder]

The value of the PMSWSTAT.TRIST bit determines the behavior of the pads.

When you have HWCFG[6] = 0 latched on a Cold PORST this places the pads in tristate mode and any subsequent run-time Warm Reset/ System Reset / Application Reset of the hardware will maintain this pad behavior.

Changing PMSWCR0.TRISTREQ bit will update the PMSWSTAT.TRIST bit and respectively the pad behavior.