Hi Lucas,
The Shared Resource Interconnection (SRI) is the high speed system bus for TriCore1.6.x CPU.The central module of the interconnect is the XBar_SRI which connects all components in one SRI system. The XBar_SRI handles, arbitrates and forwards the communication between all connected SRI-Master and SRI-Slave peripherals.
One Mater has direct access to several slave ports and one slave serves one master at the same time .Access Latency still can happen if several masters are using the same slave . There is no access latency when different slaves are addressed.
SRI crossbar has a high bandwidth with 64 bit wide data bus and can operate at maximum system frequency ,Example 200Mhz for Aurix™ TC27x MCU.
Best regards,
Mr. AURIX™
