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User17612
Level 4
Level 4
First like received
Hi all,

What happens when reading and flash operation (e.g. erasing/programming) conflict?

Best regards,
Lucas

#8042000 19449
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1 Reply
User18237
Level 5
Level 5
First solution authored First like received
Hi Lucas,

This depends on whether the flash bank to be accessing the same bank or not. "Read from flash", would mean a read access is done via the SRI bus and "Flash Operation" means the flash bank is in "BUSY" state with a command.
Case 1) Same bank; Master 1 and 2 access to same bank (e.g. PF0) according to the following table:
4074.attach
1) During its execution the Flash bank reports BUSY in FSR. In this mode read accesses to this Flash bank are refused with a bus error or the ready is suppressed until BUSY clears.
This can be configured (see FCON.STALL). At the end of an operation the Flash bank returns to read mode and BUSY is cleared.
2) Bus error occurs for write access to DF0 address range when normal command interpreter is busy with a command. Bus error occurs for write access to DF1 address range when HSM command interpreter is busy with a command.
In case of flash commands conflict by the CPU and HSM, please see "Time Slice Control".
Case 2) Different bank; Master 1 and 2 access to different bank (e.g. PF0 and PF1) according to the following table:
4075.attach

Best regards,
Mr. AURIX™
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