AURIX™ Forum Discussions

[User22771]

Hi

am using Aurix TC365, have set DCache to standby (DCBYP) and CPU_DCMAP to "Memory-mapped" but still failed to visit the SRAM reserved for DCache, have i missed anything?

[cwunder]

Did you note these considerations?
- The mapping of cache and tag memories to the TriCore address space is controlled by the MTU_MEMMAP register
- TAG SRAMs are not meant to be used as general SRAMs and can be accessed only with single data access and only with 64 bit aligned address.

[User22771]

cwunder wrote:
Did you note these considerations?
- The mapping of cache and tag memories to the TriCore address space is controlled by the MTU_MEMMAP register
- TAG SRAMs are not meant to be used as general SRAMs and can be accessed only with single data access and only with 64 bit aligned address.

Sorry have not told everything in my first Post: DCache was disabled, MTU was ON and CPU0_DCMAP in MTU_MEMMAP was set to Memory-mapped, wanted to read out the first Byte at the start address of CPU0 DCache, eg. for TC365 should be 0x7003C000. Have not noticed the announcement about "only with 64 bit aligned address" in User Manual
And when then how to interrupt 0x7003C000 to 64 bit aligned address?