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ysqcn
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Hi, 

On Aurix TC377 triboard, I use bellow code to do a reboot (application reset), after that I stop on my first code line, and check SMU_AGx registers. However SMU_AG6/7 get unexpected value: please check bellow snapshot for comparison. 

Any reason that SMU_AG6/7 value is not as expected?

 

Reboot code

 

 

206      /* Get the CPU EndInit password */
207      uint16_t CPUEndinitPw = IfxScuWdt_getCpuWatchdogPassword();
208
209      /* Configure the request trigger in the Reset Configuration Register */
210      IfxScuRcu_configureResetRequestTrigger(IfxScuRcu_Trigger_sw, IfxScuRcu_ResetType_application);
211
212      /* Clear CPU EndInit protection to write in the SWRSTCON register of SCU */
213      IfxScuWdt_clearCpuEndinit(CPUEndinitPw);
214
215      /* Trigger a software reset based on the configuration of RSTCON register */
216      IfxCpu_triggerSwReset();

 

 

.  

Register comparison: left is the expected values from safety manual. right is actual values on my TC377 triboard:

 

The UCB_DFLASH configuration from memtool

ysqcn_1-1696944526526.png

Thank you very much.

 

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1 Solution
Jeremy_Z
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Hi @ysqcn 
After digging deeper, in the errata document, there's an item: SMU_TC.H012 Handling of SMU alarms ALM7[1] and ALM7[0], which demonstrates the way for handling, of course, include the related registers.
Please refer to it for details.
BR,
Jeremy

View solution in original post

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Jeremy_Z
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Hi @ysqcn 
Can you share the screenshot of the SMU_ADi registers too?
BR,
Jeremy

 

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ysqcn
Level 2
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Hi,

 

ADi are all zero. AG6 is zero now (in my last post, I might use jtag to reset)

ysqcn_1-1697016280616.png

 

 

 

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Jeremy_Z
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Hi @ysqcn 
It should consider the debug tool connection in the case, I'd like to suggest you print the values of the set of SUM_AG register via the UART interface in the code to verification.
BR,
Jeremy

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Nambi
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Hi,

It is possible that the alarms were reported after a different type of reset(cold/warm PORST or system reset) and were not cleared before the application reset was triggered. You can check if you clear these alarms before triggering application reset. Safety manual contents(description, images) are covered under NDA. It cannot be shared or discussed in the public community. 

Best Regards.

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ysqcn
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Thanks for the reply @Nambi  & @Jeremy_Z 

I did some code refine and disconnect the jtag debugger (close all debugger apps)

Now I get AG7[1] set, and from document, it looks to have something with FSIRAM (my board is tc377 triboard which doesn't have LMU).

Now my question is for how to do further debug:

1. how to get next level details about this FSIRAM error? 

2. how to clear this error?  Use MODULE_MTU.MC[?], but I don't find a proper index for FSI from ILLD IfxMtu_MbistSel enum

 

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Jeremy_Z
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Hi @ysqcn 
1) Firstly, TC377 contains the LMU.
2) The following figure demonstrates the source of triggering the ALM7[1].

2023-10-13_10h51_43.png
3) Please follow the 13.5 Safety Measures section to handle the ALM7[1].
BR,
Jeremy

 

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ysqcn
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Level 2
First like received 5 replies posted 10 sign-ins

@Jeremy_Z wrote:

Hi @ysqcn 
1) Firstly, TC377 contains the LMU.
2) The following figure demonstrates the source of triggering the ALM7[1].

2023-10-13_10h51_43.png
3) Please follow the 13.5 Safety Measures section to handle the ALM7[1].
BR,
Jeremy

 


Yes. I know the source of AG7[1].

Now my question is regarding to FSI RAM.

I refer to example MTU_MBIST_1_KIT_TC375_LK/

From bellow definition, there is no FSI_RAM related. DAM0/mimiMcds are there.

Could you point out if there is any misunderstanding?

typedef enum
{
    IfxMtu_MbistSel_none        = -1,
    IfxMtu_MbistSel_cpu0Dspr    = 0,
    IfxMtu_MbistSel_cpu0Dtag    = 1,
    IfxMtu_MbistSel_cpu0Pspr    = 2,
    IfxMtu_MbistSel_cpu0Ptag    = 3,
    IfxMtu_MbistSel_cpu0Dlmu    = 4,
    IfxMtu_MbistSel_cpu1Dspr    = 5,
    IfxMtu_MbistSel_cpu1Dtag    = 6,
    IfxMtu_MbistSel_cpu1Pspr    = 7,
    IfxMtu_MbistSel_cpu1Ptag    = 8,
    IfxMtu_MbistSel_cpu1Dlmu    = 9,
    IfxMtu_MbistSel_cpu2Dspr    = 10,
    IfxMtu_MbistSel_cpu2Dtag    = 11,
    IfxMtu_MbistSel_cpu2Pspr    = 12,
    IfxMtu_MbistSel_cpu2Ptag    = 13,
    IfxMtu_MbistSel_cpu2Dlmu    = 14,
    IfxMtu_MbistSel_cpu0Dspr1   = 34,
    IfxMtu_MbistSel_cpu1Dspr1   = 35,
    IfxMtu_MbistSel_dam0        = 38,
    IfxMtu_MbistSel_dma         = 41,
    IfxMtu_MbistSel_miniMcds    = 42,
    IfxMtu_MbistSel_gtmFifo     = 53,
    IfxMtu_MbistSel_gtmMcs0Fast = 55,
    IfxMtu_MbistSel_gtmMcs1Fast = 57,
    IfxMtu_MbistSel_gtmDpll1a   = 58,
    IfxMtu_MbistSel_gtmDpll1b   = 59,
    IfxMtu_MbistSel_gtmDpll2    = 60,
    IfxMtu_MbistSel_mcan0       = 62,
    IfxMtu_MbistSel_mcan1       = 63,
    IfxMtu_MbistSel_psi5        = 65,
    IfxMtu_MbistSel_eray0Obf    = 66,
    IfxMtu_MbistSel_eray0IbfTbf = 68,
    IfxMtu_MbistSel_eray0Mbf    = 70,
    IfxMtu_MbistSel_scrXram     = 77,
    IfxMtu_MbistSel_scrIram     = 78,
    IfxMtu_MbistSel_ethermacRx  = 82,
    IfxMtu_MbistSel_ethermacTx  = 83
} IfxMtu_MbistSel;

 

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Jeremy_Z
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Hi @ysqcn 
After checking, the FSI RAM is not accessible by the user. It is used only to configure the FLASH. It is not possible to test it using the MTU because the FSI takes control of its memory controller after startup.
However, an ECC error in the FSI would be detected in another way since it will cause a faulty FLASH configuration.
BR,
Jeremy

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ysqcn
Level 2
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@Jeremy_Z wrote:

Hi @ysqcn 
After checking, the FSI RAM is not accessible by the user. It is used only to configure the FLASH. It is not possible to test it using the MTU because the FSI takes control of its memory controller after startup.
However, an ECC error in the FSI would be detected in another way since it will cause a faulty FLASH configuration.
BR,
Jeremy


@Jeremy_Z 

Yes. Would you point out how to check the detailed information of this FSI ECC error (e.g. is there any register to show the cause, or the address that cause this ECC error?

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Jeremy_Z
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Hi @ysqcn 
After digging deeper, in the errata document, there's an item: SMU_TC.H012 Handling of SMU alarms ALM7[1] and ALM7[0], which demonstrates the way for handling, of course, include the related registers.
Please refer to it for details.
BR,
Jeremy

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ysqcn
Level 2
Level 2
First like received 5 replies posted 10 sign-ins

@Jeremy_Z 

1) Firstly, TC377 contains the LMU.

I refer to https://www.infineon.com/dgdl/Infineon-AURIX_TC37x-UserManual-v02_00-EN.pdf?fileId=5546d4627506bb320...

Can't it apply to TC377?

ysqcn_0-1697181318940.png

 

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ysqcn
Level 2
Level 2
First like received 5 replies posted 10 sign-ins

After digging deeper, in the errata document, there's an item: SMU_TC.H012 Handling of SMU alarms ALM7[1] and ALM7[0], which demonstrates the way for handling, of course, include the related registers.
Please refer to it for details.

Thank you for this information

Translation_Bot
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Does it work for you after processing according to the recommended treatment method in SMU _TC.H012? I can't remove ALM7 by following the recommended actions [1]

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/%E5%9C%A8-TC377-%E4%B8%89%E6%9D%BF%E4%B8%8A%E9%87%8D%E7%BD%AE%E5%BA%94%E7%94%A8%E7%A8%8B%E5%BA%8F%E5%90%8E-SMU-AG6-7-%E4%B8%AD%E5%87%BA%E7%8E%B0%E6%84%8F%E5%A4%96%E5%80%BC/m-p/644574

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