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robs1
Level 4
Level 4
100 sign-ins 50 replies posted First solution authored

How can I set the CMU clock 0 (for ATOM) to 200 MHz??

My code lines doesn't work.

Can you help me?

1 Solution
Jeremy_Z
Moderator
Moderator
Moderator
250 sign-ins 100 likes received 750 replies posted

Hi @robs1

Please check the below condition is met before configuring the CLS0_CLK_DIV bits.

2023-05-25_10h00_57.png
BR,
Jeremy 

View solution in original post

9 Replies
Jeremy_Z
Moderator
Moderator
Moderator
250 sign-ins 100 likes received 750 replies posted

Hi @robs1 

Please check the code to ensure the CLS0_CLK runs at 200 MHz.

2023-05-24_11h08_06.png

BR,

Jeremy

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robs1
Level 4
Level 4
100 sign-ins 50 replies posted First solution authored

Hi, thank you!

How can I set this clock to 200 MHz? By which line of code 

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Jeremy_Z
Moderator
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250 sign-ins 100 likes received 750 replies posted

Hi @robs1 
Firstly, I'd like to suggest you acquire the frequency of the CLS0_CLK by using the below IfxGtm_getClusterFrequency() function, then it can provide the clues to adjust its frequency.
It doesn't exist such a function that can set the CLS0_CLK to an expected frequency in one action.

float32 IfxGtm_getClusterFrequency(Ifx_GTM *gtm, IfxGtm_Cluster cluster)
{
    float32 Freq;
    uint8   clsDiv = ((gtm->CLS_CLK_CFG.U) >> (cluster * 2)) & 0x3;

    if (clsDiv == 0)
    {
        Freq = 0.0; /* cluster is disabled - return 0 */
    }
    else
    {
        Freq = IfxGtm_getSysClkFrequency() / clsDiv;
    }

    return Freq;
}


BR,
Jeremy

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robs1
Level 4
Level 4
100 sign-ins 50 replies posted First solution authored

Yes, I found that its value is 100 MHz, so I need to set it to 200 MHz but adding this


gtm_ptr->CLS_CLK_CFG.B.CLS0_CLK_DIV=1;

the code doesn't run.

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Jeremy_Z
Moderator
Moderator
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250 sign-ins 100 likes received 750 replies posted

Hi @robs1 ,

Yes, setting the CLS0_CLK_DIV bits = 01 should work.

And I don't know the meaning of 'the code doesn't run'.

BR,

Jeremy

robs1
Level 4
Level 4
100 sign-ins 50 replies posted First solution authored

gtm_ptr->CLS_CLK_CFG.B.CLS0_CLK_DIV=1;
gtm_ptr->CMU.GCLK_NUM.B.GCLK_NUM = 0x1;
gtm_ptr->CMU.GCLK_NUM.B.GCLK_NUM = 0x1; // write twice to be sure, taken from specs
gtm_ptr->CMU.GCLK_DEN.B.GCLK_DEN = 1;
gtm_ptr->CMU.CLK[0].CTRL.B.CLK_CNT = 0;
gtm_ptr->CMU.CLK_EN.B.EN_CLK0 = 0x2;

I wrote like this but the code can’t be uploaded in the board so it is “suspended” at the second code line

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Jeremy_Z
Moderator
Moderator
Moderator
250 sign-ins 100 likes received 750 replies posted

Hi @robs1

Please check the below condition is met before configuring the CLS0_CLK_DIV bits.

2023-05-25_10h00_57.png
BR,
Jeremy 

robs1
Level 4
Level 4
100 sign-ins 50 replies posted First solution authored

Thank you , now it works!

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robs1
Level 4
Level 4
100 sign-ins 50 replies posted First solution authored

gtm_ptr->CTRL.B.RF_PROT=0;
gtm_ptr->CLS_CLK_CFG.B.CLS0_CLK_DIV=01;
gtm_ptr->CMU.GCLK_NUM.B.GCLK_NUM = 0x1;
gtm_ptr->CMU.GCLK_NUM.B.GCLK_NUM = 0x1; // write twice to be sure, taken from specs
gtm_ptr->CMU.GCLK_DEN.B.GCLK_DEN = 1;
gtm_ptr->CMU.CLK[0].CTRL.B.CLK_CNT = 0;
gtm_ptr->CMU.CLK_EN.B.EN_CLK0 = 0x2;

 

I wrote like this, now the code is upload successfully but when I check with:

clockff=IfxGtm_Cmu_getClkFrequency(&MODULE_GTM, IfxGtm_Cmu_Clk_0, TRUE);

 

I obtain a clockff of 100 MHz still.... where am I wrong? 

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