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Nov 02, 2020
06:03 AM
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Nov 02, 2020
06:03 AM
Hello everyone,
I am trying to configure an ASCLIN UART Interface. Unfortunately I am running into a trapbus instruction. I have already consulted tasking on this issue. They have redirected me to here, you can take a look at the case:
https://supportcenter.tasking.com/#CaseDetails/E96675E8-6264-C2A6-C216-0CF93003EDFC
I have tried writing into the registers using different ways. Either only selected bits or the whole register. Also using the defines out of the IfxAsclin_regdef.h / IfxAsclin_reg.h headers. Unfortunately I always run into a trapbus error.
I guess there is maybe just another bit that needs to be cleared/set. Any help will be appreciated.
Thanks.
I am trying to configure an ASCLIN UART Interface. Unfortunately I am running into a trapbus instruction. I have already consulted tasking on this issue. They have redirected me to here, you can take a look at the case:
https://supportcenter.tasking.com/#CaseDetails/E96675E8-6264-C2A6-C216-0CF93003EDFC
I have tried writing into the registers using different ways. Either only selected bits or the whole register. Also using the defines out of the IfxAsclin_regdef.h / IfxAsclin_reg.h headers. Unfortunately I always run into a trapbus error.
I guess there is maybe just another bit that needs to be cleared/set. Any help will be appreciated.
Thanks.
- Tags:
- IFX
4 Replies
Nov 02, 2020
07:46 AM
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Nov 02, 2020
07:46 AM
You need an account to see the details of the Tasking issue - please could you paste the details here.
Nov 02, 2020
10:11 AM
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Nov 02, 2020
10:11 AM
Did you enable the ASCLIN peripheral first with something like this?
By default, the clock for most AURIX peripherals is off, and accessing any register besides CLC will cause a bus error.
// enable the peripheral
IfxScuWdt_clearGlobalEndinit( IfxScuWdt_getGlobalEndinitPassword() );
MODULE_ASCLIN0->CLC.U = 0;
IfxScuWdt_setGlobalEndinit( IfxScuWdt_getGlobalEndinitPassword() );
By default, the clock for most AURIX peripherals is off, and accessing any register besides CLC will cause a bus error.
Nov 02, 2020
10:27 AM
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Nov 02, 2020
10:27 AM
Have a look to section 8.1.4.1 Clock Control Register CLC
In your code you should move the CLC enabling... Before you access any other SFR in the ASCLIN
Write operations to the non CLC registers of disabled modules are not allowed. However, the CLC of a disabled module can be written. An attempt to write to any of the other writable registers of a disabled module except CLC will cause the corresponding Bus Control Unit (BCU) to generate a bus error.
In your code you should move the CLC enabling... Before you access any other SFR in the ASCLIN
void Init_asclinDrv(void){
uint16 passwd = IfxScuWdt_getCpuWatchdogPassword();
IfxScuWdt_clearCpuEndinit(passwd);
pAsclin->CLC.B.DISR = 0U; // disable module control
pAsclin->CLC.B.EDIS = 1U; // disable disable listening to sleep mode
Nov 20, 2020
06:35 AM
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Nov 20, 2020
06:35 AM
Sorry for my late reply but unfortunately I did not receive any information about all the replies.
To clarify, yes I was unlocking the write by writing the password. Here is an update on what I found. The DEADD Register helped me to identify that the trap was caused by writing into csr Register, writing 0 for the clock selection as it already was 0. After avoiding this, the initialization of the module works fine.
To clarify, yes I was unlocking the write by writing the password. Here is an update on what I found. The DEADD Register helped me to identify that the trap was caused by writing into csr Register, writing 0 for the clock selection as it already was 0. After avoiding this, the initialization of the module works fine.