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oneday
Level 2
Level 2
First like received 10 sign-ins First solution authored

Dear experts:

The  description about “Time Check Password” as follow:

 If time checking is enabled (WDTxSR.TCS=1) the REL field of the WDTxCON0 register must be written with an
inverted (bit flipped) estimate of the current WDT count value. The acceptable margin of error of this estimate (in
WDT clock periods) is specified by the value of WDTxSR.TCT. If the written estimate is outside the range
WDTxSR.TIM +/- WDTxSR.TCT, then an SMU alarm condition is indicated. This mechanism can provide a check of
the elapsed program execution time since the last WDT restart. Note that a Time Check comparison is still
required for a Password or Check Access while the WDT is operating in Time-Out mode (e.g. After accessing
ENDINIT-protected registers).

According to the above description:whether REL should be computed as such?

For example:WDTxSR.TCS=1 ,and current WDT count value = 0xFF0F;WDTxSR.TCT = 0xF

step1:Calculate inverted estimate value according to  WDT count value : estimate value=0x00FF;

step2:    Calculate WDTxSR.TIM +/- WDTxSR.TCT: 0xFF00 ~ 0xFF1E

step3:  write estimate value to REL. But the  estimate value(0x00FF) is always out off the range  0xFF00 ~ 0xFF1E,so how to correctly use "Time Check Password" to implement "Password Access to WDTxCON0".

Is the above example correct? If not, could you provide the correct example or code?

Looking forward your reply.

 

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1 Solution
Nambi
Moderator
Moderator
Moderator
First like given 25 likes received 50 solutions authored

Hi,

When the time check is enabled, the register "WDTxSR.TCS" representing the time check status of the WDT will be 1. During the password access, "WDTxCON1.REL" needs to be written with an inverted WDT counter estimate value. Tolerance to this value is configured in "WDTxCON1.TCTR." This feature can not only be used to allow the firmware to service the WDT before overflowing but also, the firmware should have the correct estimate of the current WDT counter value.

For example, Consider that the "WDTxCON1.REL" register is configured as 0xE000, which makes the WDT period 1.3 s. Consider the time check tolerance to be configured as 0x7F.

Consider that the service of the watchdog is done after an estimated elapsed time(possible firmware execution time before the watchdog servicing) of 1 s. Here, the estimated current watchdog counter value should be around 0xF800. So the inverted value 0x07FF can be written to the WDTxCON1.REL during the password access step while servicing the watchdog.

0xF800 should be equal to the actual current watchdog counter value +/-the acceptable margin of error(WDTxSR.TIM +/- WDTxSR.TCT . Here, 0x7F configured in WDTxSR.TCT) of this estimate (in WDT clock periods). If the estimate is outside the range, an SMU alarm is indicated.

Best Regards.

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3 Replies
Nambi
Moderator
Moderator
Moderator
First like given 25 likes received 50 solutions authored

Hi,

Please refer to the ADS(Aurix Development Studio) example Watchdog_1_KIT_TC397_TFT APIs from the expert training.

https://www.infineon.com/cms/en/product/promopages/aurix-expert-training/

Best Regards.

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oneday
Level 2
Level 2
First like received 10 sign-ins First solution authored

hello, 

I have already tested the example "Watchdog_1_KIT_TC397_TFT",but this example does not  contain the  "Time Check Password" use case and APIs. Could you give me some use case about "Time Check Password".Thanks a lot.

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Nambi
Moderator
Moderator
Moderator
First like given 25 likes received 50 solutions authored

Hi,

When the time check is enabled, the register "WDTxSR.TCS" representing the time check status of the WDT will be 1. During the password access, "WDTxCON1.REL" needs to be written with an inverted WDT counter estimate value. Tolerance to this value is configured in "WDTxCON1.TCTR." This feature can not only be used to allow the firmware to service the WDT before overflowing but also, the firmware should have the correct estimate of the current WDT counter value.

For example, Consider that the "WDTxCON1.REL" register is configured as 0xE000, which makes the WDT period 1.3 s. Consider the time check tolerance to be configured as 0x7F.

Consider that the service of the watchdog is done after an estimated elapsed time(possible firmware execution time before the watchdog servicing) of 1 s. Here, the estimated current watchdog counter value should be around 0xF800. So the inverted value 0x07FF can be written to the WDTxCON1.REL during the password access step while servicing the watchdog.

0xF800 should be equal to the actual current watchdog counter value +/-the acceptable margin of error(WDTxSR.TIM +/- WDTxSR.TCT . Here, 0x7F configured in WDTxSR.TCT) of this estimate (in WDT clock periods). If the estimate is outside the range, an SMU alarm is indicated.

Best Regards.