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xinlangzaihou
Level 2
Level 2
10 replies posted 5 replies posted 5 questions asked
我按照官网提供的SPI例程,先初始化Module,然后在Channel初始化时,将SPI模式配置为3(clock polarity = 1;clock phase=1)。但是此时CLK的状态仍然为低电平,只有当发送一帧数据后,CLK状态才能够变成高电平。这样的话第一帧的CLK就少了一个下降边沿,导致数据读取异常。请问该问题该该怎解决!请大佬们不吝赐教!
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11 回复数
xinlangzaihou
Level 2
Level 2
10 replies posted 5 replies posted 5 questions asked
通过查数据手册,说是在第一个idleA后(37.3.2.1 Phases of one Communication Cycle),CLK会更新极性,可是我这也第一帧开始时依然是低电平。。。
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独秀一郎
Level 5
Level 5
Welcome! 50 comments on blog 25 comments on blog
你是自发自收嘛?
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不是,TC3xx做主机,和另一个芯片通讯。第一帧读的数据不对。另一个芯片的手册上写的是使用SPI的模式3.
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高低字节顺序,采样、捕获数据沿,波特率都配置正确吗
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JET
Level 1
Level 1
应该是配置问题,查看一下PORT配置和SPI CLK的空闲状态是高还是低
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xinlangzaihou
Level 2
Level 2
10 replies posted 5 replies posted 5 questions asked
以下是SPI的初始化配置(CLK port 初始化为上拉,econ.B.CPH = 1): static void IfxQspi_Masterinit(void) { uint32 i=10000000; IfxQspi_SpiMaster_Config spiMasterConfig; IfxQspi_SpiMaster_ChannelConfig spiMasterChannelConfig; { /* create module config */ IfxQspi_SpiMaster_initModuleConfig(&spiMasterConfig, &MODULE_QSPI0); /* set the maximum baudrate */ // spiMasterConfig.base.maximumBaudrate = 10000000; /* ISR priorities and interrupt target */ spiMasterConfig.base.txPriority = ISR_PRIORITY_QSPI0_TX; spiMasterConfig.base.rxPriority = ISR_PRIORITY_QSPI0_RX; spiMasterConfig.base.erPriority = ISR_PRIORITY_QSPI0_ER; spiMasterConfig.base.isrProvider = ISR_PROVIDER_QSPI0; /* pin configuration */ const IfxQspi_SpiMaster_Pins pins = {&IfxQspi0_SCLK_P22_7_OUT, /* SCLK */ IfxPort_OutputMode_pushPull, &IfxQspi0_MTSR_P22_10_OUT, IfxPort_OutputMode_pushPull, /* MTSR */ &IfxQspi0_MRSTC_P22_6_IN, IfxPort_InputMode_pullDown, /* MRST */ IfxPort_PadDriver_cmosAutomotiveSpeed3 /* pad driver mode */ }; spiMasterConfig.pins = &pins; /* initialize module */ IfxQspi_SpiMaster_initModule(&g_QspiCpu.drivers.spiMaster, &spiMasterConfig); } { /* create channel config */ IfxQspi_SpiMaster_initChannelConfig(&spiMasterChannelConfig, &g_QspiCpu.drivers.spiMaster); /* set the baudrate for this channel */ spiMasterChannelConfig.base.baudrate = 10000000; /*PLC used SPI mode 3(CPOL = 1,CPHA = 1)*/ spiMasterChannelConfig.base.mode.shiftClock = SpiIf_ShiftClock_shiftTransmitDataOnLeadingEdge; spiMasterChannelConfig.base.mode.clockPolarity = SpiIf_ClockPolarity_idleHigh; const IfxQspi_SpiMaster_Output slsOutput = {&IfxQspi0_SLSO10_P22_11_OUT, IfxPort_OutputMode_pushPull, IfxPort_PadDriver_cmosAutomotiveSpeed1}; spiMasterChannelConfig.sls.output.pin = slsOutput.pin; spiMasterChannelConfig.sls.output.mode = slsOutput.mode; spiMasterChannelConfig.sls.output.driver = slsOutput.driver; /* initialize channel */ IfxQspi_SpiMaster_initChannel(&g_QspiCpu.drivers.spiMasterChannel, &spiMasterChannelConfig); }
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这个是我的SPI初始化配置: /** rief Qspi Master initilisation * * This function initialises Qspi0 in master mode. */ static void IfxQspi_Masterinit(void) { uint32 i=10000000; IfxQspi_SpiMaster_Config spiMasterConfig; IfxQspi_SpiMaster_ChannelConfig spiMasterChannelConfig; { /* create module config */ IfxQspi_SpiMaster_initModuleConfig(&spiMasterConfig, &MODULE_QSPI0); /* set the maximum baudrate */ // spiMasterConfig.base.maximumBaudrate = 10000000; /* ISR priorities and interrupt target */ spiMasterConfig.base.txPriority = ISR_PRIORITY_QSPI0_TX; spiMasterConfig.base.rxPriority = ISR_PRIORITY_QSPI0_RX; spiMasterConfig.base.erPriority = ISR_PRIORITY_QSPI0_ER; spiMasterConfig.base.isrProvider = ISR_PROVIDER_QSPI0; /* pin configuration */ const IfxQspi_SpiMaster_Pins pins = {&IfxQspi0_SCLK_P22_7_OUT, /* SCLK */ IfxPort_OutputMode_pushPull, &IfxQspi0_MTSR_P22_10_OUT, IfxPort_OutputMode_pushPull, /* MTSR */ &IfxQspi0_MRSTC_P22_6_IN, IfxPort_InputMode_pullDown, /* MRST */ IfxPort_PadDriver_cmosAutomotiveSpeed3 /* pad driver mode */ }; spiMasterConfig.pins = &pins; /* initialize module */ IfxQspi_SpiMaster_initModule(&g_QspiCpu.drivers.spiMaster, &spiMasterConfig); } { /* create channel config */ IfxQspi_SpiMaster_initChannelConfig(&spiMasterChannelConfig, &g_QspiCpu.drivers.spiMaster); /* set the baudrate for this channel */ spiMasterChannelConfig.base.baudrate = 10000000; /*PLC used SPI mode 3(CPOL = 1,CPHA = 1)*/ spiMasterChannelConfig.base.mode.shiftClock = SpiIf_ShiftClock_shiftTransmitDataOnLeadingEdge; spiMasterChannelConfig.base.mode.clockPolarity = SpiIf_ClockPolarity_idleHigh; const IfxQspi_SpiMaster_Output slsOutput = {&IfxQspi0_SLSO10_P22_11_OUT, IfxPort_OutputMode_pushPull, IfxPort_PadDriver_cmosAutomotiveSpeed1}; spiMasterChannelConfig.sls.output.pin = slsOutput.pin; spiMasterChannelConfig.sls.output.mode = slsOutput.mode; spiMasterChannelConfig.sls.output.driver = slsOutput.driver; /* initialize channel */ IfxQspi_SpiMaster_initChannel(&g_QspiCpu.drivers.spiMasterChannel, &spiMasterChannelConfig); } }
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这个代码格式为什么编辑的时候好好的,提交以后所有的空格和换行就没有了,还有怎样可以上传图片?
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我认为也可能是配置问题。现在的现象是将SPI初始化为CLK空闲为高电平,但是实际CLK是低电平,发完一帧数据后CLK空闲就是高电平了。。。 让我疑惑的一点是CLK引脚初始化为上拉状态,是在Module初始化的;而SPI模式(CLK的极性)是在channel中初始化的,初始化完极性后,CLK的状态并没有改变???所以现在我也不知道从哪下手解决这个问题了。。。 望大神们不吝赐教!!!
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该问题已经解决,通过将增加IDEL时间(spiMasterChannelConfig.base.mode.csInactiveDelay= 1;),在发送数据前可以看到CLK的时钟信号变为高电平。
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JackLiu
Level 3
Level 3
5 comments on blog First comment on blog 25 replies posted
应该是配置问题,查看一下SPI CLK的空闲状态是高还是低
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