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SteffenR
Level 1
Level 1
First reply posted First question asked Welcome!

Hello,

I'm using the TC3E7 Starterkit with the Hightec Development Platform.
We want to create CAN drivers for our J1939 and CANopen Stacks .


Because I didn't found specific TC3E7 initializations I'm using the TC387 settings.
The initialization is only minimal. The base code comes from a blinky and works
with the onboard LEDs and the STM timer.

I activated the 3 clocks for the MCMCAN and I want to use the CAN00.

Everytime it seems, that I can write one time to a registers, but a second one creates an Trap 4.

In my special case now  I want to start the initialization with a kernel reset.

	volatile Ifx_CAN *const module_can0 = (Ifx_CAN*)0xF0200000u;
	module_can0->KRST1.U = 1;
	module_can0->KRST0.U = 1; /* Trap 4 */
	while (module_can0->KRST0.B.RSTSTAT == 0)
		;
	module_can0->KRSTCLR.B.CLR = 1;

 

In case I start with a

	/* no suspend */
	module_can0->CLC.U = 0u;

before the sequence above the Trap 4 is called with the KRST1 access. That's why I mean it is everytime the second write access.

Do I have to activate some more before I have access to the MCMCAN?

Thank you

Best regards

Steffen

 

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1 Solution
MoD
Employee
Employee
50 likes received 500 replies posted 100 solutions authored

The register CLC, KRST0, KRST1 and KRSTCLR are endinit protected. Before write to this registers you must make sure that corresponding CPU endinit is cleared. 

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2 Replies
MoD
Employee
Employee
50 likes received 500 replies posted 100 solutions authored

The register CLC, KRST0, KRST1 and KRSTCLR are endinit protected. Before write to this registers you must make sure that corresponding CPU endinit is cleared. 

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SteffenR
Level 1
Level 1
First reply posted First question asked Welcome!

Thank you very much.

I misinterpreted the unlock_wdtcon() as watchdog sequences.

Now, it's works.

Best regards

Steffen

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