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Noblesse
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Hello Community,
I m working on a Vector FBL on Tc3E7 and i m trying to communicate with an SBC using QSPI4.

I configured the Baudrate to 500000 and the fQSPI to 160Mhz.

I m using Mcal SPI driver.

using the logic analyzer(screenshot below), I saw that the clock is sent out with the correct frequency, the MOSI data is correct, the chipselect is also triggered correctly and there is data returned from SBC in the MISO line.

However, the SPI does not read the data in MISO line and returns FFFFF intead.

Do you have any hints what could be the issue here ?

Noblesse_0-1673370499682.png

 

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dw
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https://github.com/Infineon/AURIX_code_examples/blob/master/code_examples/SPI_CPU_1_KIT_TC397_TFT/Cp...

Could you please try QSPI2 and QSPI3?

Above code is example for your reference.

dw

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dw
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Please use duplex mode to try.

The QSPI operates in one of three modes regarding the direction of the communication and depending whether the transmission and the reception appear simultaneously or not: duplex, half-duplex and simplex mode.
This gives six possible combinations for the operating mode of the QSPI: master duplex, half-duplex, and simplex; slave duplex, half-duplex, and simplex.

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Noblesse
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Hello DW,
Thank you for your inputs.
Sadly, i m integrating on a remote customer HW, and only QSPI4 is used, so I cannot experiment with other QSPIs.

I m using MCal spi, and according to the user manual :
"The SPI driver operates in the master and full duplex communication modes only. The driver supports
synchronous and asynchronous communication supporting Level-0, Level-1 and Level-2 type configurations."

So it seems i configured master full duplex and Level0.

What confuses me is the bus trace looks ok, but it seems i can't read the MISO, is there any special register that i have to check, or hint to where i can look for , as it doesn t make sense for me why it cannot read the data that seem to be correct.

 

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dw
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It's useful if you post all the registers' value of QSPI.

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Noblesse
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Hello, 
Here is the QSPI4 registers after i sent the first command :

Noblesse_0-1673543025611.png

 

Noblesse_1-1673543038015.png

 

 

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dw
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QSPI2_ACCEN0	0xffffffff		
QSPI2_ACCEN1	0x0		
QSPI2_BACON	0x17224025		
QSPI2_BACONENTRY	0x0		
QSPI2_CAPCON	0x0		
QSPI2_CLC	0x8		
QSPI2_DATAENTRY0	0x0		
QSPI2_DATAENTRY1	0x0		
QSPI2_DATAENTRY2	0x0		
QSPI2_DATAENTRY3	0x0		
QSPI2_DATAENTRY4	0x0		
QSPI2_DATAENTRY5	0x0		
QSPI2_DATAENTRY6	0x0		
QSPI2_DATAENTRY7	0x0		
QSPI2_ECON0	0x1450		

QSPI2_ECON1	0x47c4		
QSPI2_ECON2	0x1450		
QSPI2_ECON3	0x1450		
QSPI2_ECON4	0x1450		
QSPI2_ECON5	0x1450		
QSPI2_ECON6	0x1450		
QSPI2_ECON7	0x1450		
QSPI2_FLAGSCLEAR	0x0		
QSPI2_GLOBALCON	0x21003c00		
QSPI2_GLOBALCON1	0x7ff		
QSPI2_ID	0xc0c005		
QSPI2_KRST0	0x0		
QSPI2_KRST1	0x0		
QSPI2_KRSTCLR	0x0		
QSPI2_MC	0x0		
QSPI2_MCCON	0x0		
QSPI2_MIXENTRY	0x0		
QSPI2_OCS	0x0		
QSPI2_PISEL	0x1		
QSPI2_RXEXITD	0xffffffff		
QSPI2_SSOC	0x20000		
QSPI2_STATUS	0x4401e00		
QSPI2_STATUS1	0x0		
QSPI2_XXLCON	0x0		

 

 

Above is my QSPI2 register value for your reference.

dw_0-1673599062572.png

 

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Noblesse
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Did you notice any unusual settings in my config, I think, as the baudrate requirement are different for you and me, it's not expected to have the same config.

Also, as I'm using Tricore MCAL spi driver, I expect it to write the correct registers, and explained, the transmit works fine, but just the reception in the miso.
I thought it might be a pin config issue, voltage level or something like that, I played with Cmos and TTL levels, no change.

What I noticed also, that the RXFIFO level is set to one when we transmit something and before we read the REXIT register, so we received something, but it s read FFFFF when the logic analyzer shows otherwise, I don t know yet.

Noblesse_0-1673619216492.png

 

Lautherbach doesn t show me the content of the ENtry and REXIT registers, so i don t know if there is anything inside, is this normal ?

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dw
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This issue is reported internally for QSPI4. If possible, please use QSPI0/1/2/3 to try.

Noblesse
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Hi DW,
unfortunately, the SBC is soldered to Port 33 using pins 9, 11, 12 and 13 so we can t change QSPI4 without redesigning the board.

But does your statement mean that it is a known issue for QSPI4 in TC3E7 and there is an eratta for it? or did you report my issue internally, for me to know what to report to project management?  
Thank you very much!

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Noblesse
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Hi Dw,
I don t know what I did, but know the SPI communication is working!

Thank you very much for your kind support!

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dw
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Hi Noblesse, It's better to compare the project source file previous one and currently working one. Then will know if any settings impacts.

dw

 

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