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User20322
Level 1
Level 1
Hi,

We set the QSPI4 of clock from 1MHz to 4MHz, but the clock duty from 50% change to 60%.
have any register can be set the duty?

BR,
Tony
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4 Replies
Darren_Galpin
Employee
Employee
First solution authored First like received
Hi Tony - you can control the clock source and divide ratio via CCUCON1, but not the duty cycle.
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NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
After the CCU, QSPI timing depends on the QSPI global clock (QSPIx_GLOBALCON.TQ). The duty cycle then depends on the A/B/C segment timing in the ECONz register: see Figure 465 SCLKO Duty Cycle and the Rx Data Sampling Point Relative to SCLKO, in Master Mode on page 1701 of AURIXTC3XX_um_part2_v1.6.pdf. Note that version 1.6 is hot off the press as of yesterday.
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cwunder
Employee
Employee
10 likes given 100 solutions authored 5 likes given
The ECONx register controls the Duty Cycle and is described in the user's manual. Here are some pictures that consolidate how to set the baudrate and dutycycle.

4648.attach
4649.attach
4650.attach
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User20322
Level 1
Level 1
Hi All,

Thanks for your comment, I will try to modifyde code and testing.
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