Sep 25, 2020
03:15 AM
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Sep 25, 2020
03:15 AM
Hi,
We set the QSPI4 of clock from 1MHz to 4MHz, but the clock duty from 50% change to 60%.
have any register can be set the duty?
BR,
Tony
We set the QSPI4 of clock from 1MHz to 4MHz, but the clock duty from 50% change to 60%.
have any register can be set the duty?
BR,
Tony
- Tags:
- clock duty
- IFX
- qspi
4 Replies
Sep 25, 2020
03:42 AM
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Sep 25, 2020
03:42 AM
Hi Tony - you can control the clock source and divide ratio via CCUCON1, but not the duty cycle.
Sep 25, 2020
07:02 AM
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Sep 25, 2020
07:02 AM
After the CCU, QSPI timing depends on the QSPI global clock (QSPIx_GLOBALCON.TQ). The duty cycle then depends on the A/B/C segment timing in the ECONz register: see Figure 465 SCLKO Duty Cycle and the Rx Data Sampling Point Relative to SCLKO, in Master Mode on page 1701 of AURIXTC3XX_um_part2_v1.6.pdf. Note that version 1.6 is hot off the press as of yesterday.
Sep 25, 2020
07:13 AM
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Sep 25, 2020
07:13 AM
The ECONx register controls the Duty Cycle and is described in the user's manual. Here are some pictures that consolidate how to set the baudrate and dutycycle.
Sep 29, 2020
04:57 AM
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Sep 29, 2020
04:57 AM
Hi All,
Thanks for your comment, I will try to modifyde code and testing.
Thanks for your comment, I will try to modifyde code and testing.