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jica-zhang
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After EB software is used to configure THE WDG DRIVER clock trigger source to select STM, STM is configured in MCU to import the generated code into the project, it is found that it cannot be reset without calling Wdg_17_Scu_SetTriggerCondition (using UDE and Lauterbach debugging tools).  Check the repeatedly repeated 0xFF00-0xFFFF count of TIM bit in the SCU_WDTCPU0SR register. The value of SCU_WDTCPUOCON0 is 0XFF85.  May I ask what caused the failure to reset? Is there any official WDG driver test demo?  

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AMG
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Hi @jica-zhang , 

The watchdog resetting is disabled by the debuggers (UDE and Lauterbach). If you would like to test the reset of the WDG, you would need to run your code without any debugger connected to your device. 

One way to test this, would be to have an LED blinking at a high frequency while the WDG is enabled. At the moment of the watchdog reset, you should see the LED stop blinking and then starting to blink again. 

When it comes to configuring the SMU to reset the WDG. You need to configure the specific SMU alarm related to the WDG timeout to a specific action. The mapping of the SMU alarms can be found in the AURIX  appendix HW User Manual.

For TC39xB for instance, the SMU Alarm Group 8 Alarm 10 is dedicated to CPU0 Watchdog Timeout (see attachment). 

In the EB Tresos SMU configuration, you will want to configure this specific alarm to take the behavior you want: NMI, interrupt etc... You want to configure a reset action here. 

 

Finally, in order to allow the reset to occur, in the EB Tresos MCU configuration you will need to specify what behavior you want an SMU Reset request to take. This is managed by the field "McuSMUResetConf". More details can be found here: https://community.infineon.com/t5/AURIX/smu-reset-request-configuration-from-tresos-studio/m-p/33083... 

Once you have configured the SMU alarm and the SMU Reset behavior in the MCU editor of Tresos, try again your code without having any debugger on. You should see the WDG overflow causing an SMU alarm, and the SMU alarm causing the reset. 

 

I hope this helps get you application running properly.

Good luck 🙂 

AMG_0-1651837356939.png

 

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Di_W
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Hi jica,

If you are using MCAL, please contact related FAE accordingly.

Yes, there is a demo code for Watchdog using ADS (Aurix Development Studio).

https://github.com/Infineon/AURIX_code_examples/tree/master/code_examples/Watchdog_1_KIT_TC397_TFT

The ADS is a free development environment using Tasking free compiler.

https://www.infineon.com/aurix-expert-training/Infineon-AURIX_Watchdog_1_KIT_TC397_TFT-TR-v01_00_03-...

 

dw

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Hello, may I ask whether WDG is open to check which register?  Or whether to send an alarm and look at that register?  Which register is the count timeout?  I didn't find

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Di_W
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Please refer to 9.4 Watchdog Timers(WDT) - AURIXTC3XX_um_part1_v2.0.pdf

Below lists related registers for your reference.

WDTSCON0 Safety WDT Control Register 0
WDTCPUyCON0(y=0-5) CPUy WDT Control Register 0
WDTSCON1 Safety WDT Control Register 1
WDTCPUyCON1(y=0-5) CPUy WDT Control Register 1
WDTSSR Safety WDT Status Register
WDTTCPUySR (y=0-5) CPUy WDT Status Register
EICON0 ENDINIT Global Control Register 0
EICON1 ENDINIT Global Control Register 1
EISR ENDINIT Timeout Counter Status Register
SEICON0 Safety ENDINIT Control Register 0
SEICON1 Safety ENDINIT Control Register 1
SEISR Safety ENDINIT Timeout Status Register

 

You can refer to IfxScuWdt.c of iLLD for usage of register.https://github.com/Infineon/AURIX_code_examples/blob/288e353e583148009bd03c16d65db76370cba1af/code_e...

 

 

dw

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Could you please send a complete WDG project to 490044512@qq.com? I found it could not be downloaded on Github  

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Di_W
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FYI

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If the WDG module times out, SUM will report a timeout warning to MCU, and then SUM will notify MCU to reset.  According to my test data, after the watchdog initialization, the OE bit of the status register of not feeding the dog SCU_WDTCPU0SR is set to 1, while the OE bit of periodically feeding the dog is 0. Does that mean that we can judge whether WDG times out by OE and then pass the timeout request to SUM?  

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Di_W
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For SMU, the watchdog alarms is processed as below:

15.3.1.5.8  Watchdog Alarms in AURIXTC3XX_um_part1_v2.0.pdf

The watchdogs (WDT) timeout alarms require a special processing in order to ensure a correct microcontroller behavior if the watchdogs are not serviced by software or firmware. It shall be ensured that the microcontroller is reset after a pre-warning phase, where software can still perform some critical actions.
• Every timeout alarm shall activate an NMI
• Recovery Timer 0 shall be configured to service WDT timeout alarms for Safety WDT, CPU0 WDT, CPU1 WDT and CPU2 WDT
• Recovery Timer 1 shall be configured to service WDT timeout alarms for CPU3 WDT, CPU4 WDT and CPU5 WDT
• Recovery Timer 0 and Recovery Timer 1 timeout alarms shall be configured to issue a reset request and activate the Fault Signaling Protocol.
The aforementioned properties are implemented as reset values for the watchdog(s) timeout alarm(s) and for the recovery timer 0 and 1.

 

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Di_W
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Hello, I have tested the WDG DRIVER you proposed for me and found that it will cause reset after WDG timeout. I have checked the code and there is no function related to SMU reset. May I ask how to configure WDG timeout reset?  And could you give me your contact information?  

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Di_W
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Hi jica,

For SMU part, I have checked the default value is below, I think that's why it can reset default.

ALM8[10]-ALM8[16]: Watchdog - TC39XB_ts_appx_V2.5.1.pdf
AG8CFG0 -AG8CFG2 Reset Value is 0001 FC00 (Application Reset) - AURIXTC3XX_um_part1_v2.0.pdf

If you want to configure SMU alarm, please refer to https://community.infineon.com/t5/AURIX/TC397-wdg-Unable-to-reset/m-p/346674/highlight/true#M7330

 

dw

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Will the official WDG DEMO add SMU driver?  I can't find the SMU configuration code in the WDG driver  

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Di_W
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HI jica,

Please download SMU_Reset_Alarm_1_KIT_TC397_TFT, which is a demo code for SMU reset, you can refer to this beside WDT demo code. So far there is no a demo for both two together.

dw

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My question now is that the WDG driver you provided does not integrate SMU code, but WDG overflow can be reset during my test. According to the manual, WDG overflow will send an overflow alarm to SMU, and THEN SMU will perform the reset operation, but there is no SMU module in WDG project, but it can be reset. Why?  

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Di_W
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Hi jica,

I think the default value of SMU is watchdog reset, could you please check documents in my last reply.

dw

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你好,这是我在WDG驱动运行时配置的每个寄存器的状态。问题是WDG时序溢出后系统不会复位。 请帮忙分析一下。

jicazhang_0-1651154640795.png

 

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Di_W
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Hi jica,

Could you please check AG8CFG0 and AG8CFG2? Reset Value is 0001 FC00(Application Reset) - AURIXTC3XX_um_part1_v2.0.pdf

AG8CFG0 and AG8CFG2 is 0x0001 FC00 that means 0x5 NMI for 7 WDTs timeout

AG10CFG1 and AG10CFG2 is 0x0003 0000 that means 0x6 RESET for recovery timer0/1

dw_2-1652461389037.png

 

dw_3-1652461423317.png

dw

Excuse me.  AG8CFG0 =0x0001fc00 AG8CFG1 =0x00000000 AG8CFG2 =0x0001fc00 If SMU triggers NMI Request after WDG timeout, MCU reset can be triggered?  

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Di_W
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Hi jica,

It is using NMI, and please refer below description:

dw_0-1651742292352.png

 

 

dw

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  • Hello, can you provide the download address for all the sample codes of TC397?

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Di_W
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Hi jica,

You could download all from 

https://github.com/Infineon/AURIX_code_examples/tree/master/code_examples

dw_0-1651737284895.png

 

You should prepare an internet connection to github.com

dw

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Di_W
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dw_2-1651743974874.png

 

Please also refer to above chapter.

By default, RTC is enabled as below:

RTC
Recovery Timer Configuration (030H) Application Reset Value: 003F FF03H

dw_1-1652460873284.png

 

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Hello, smU will trigger an NMI request after time-out. The reset is directly triggered by NMI according to the official demo. May I ask how NMI triggers the reset?  Can the NMI request be reset directly?  Or do you want to configure a register?  If we want to trigger the SCU reset through the Recovery timer mode as shown in the red line, how should we configure it?  

jicazhang_0-1651822748109.png

 

 

 

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AMG
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Hi @jica-zhang , 

The watchdog resetting is disabled by the debuggers (UDE and Lauterbach). If you would like to test the reset of the WDG, you would need to run your code without any debugger connected to your device. 

One way to test this, would be to have an LED blinking at a high frequency while the WDG is enabled. At the moment of the watchdog reset, you should see the LED stop blinking and then starting to blink again. 

When it comes to configuring the SMU to reset the WDG. You need to configure the specific SMU alarm related to the WDG timeout to a specific action. The mapping of the SMU alarms can be found in the AURIX  appendix HW User Manual.

For TC39xB for instance, the SMU Alarm Group 8 Alarm 10 is dedicated to CPU0 Watchdog Timeout (see attachment). 

In the EB Tresos SMU configuration, you will want to configure this specific alarm to take the behavior you want: NMI, interrupt etc... You want to configure a reset action here. 

 

Finally, in order to allow the reset to occur, in the EB Tresos MCU configuration you will need to specify what behavior you want an SMU Reset request to take. This is managed by the field "McuSMUResetConf". More details can be found here: https://community.infineon.com/t5/AURIX/smu-reset-request-configuration-from-tresos-studio/m-p/33083... 

Once you have configured the SMU alarm and the SMU Reset behavior in the MCU editor of Tresos, try again your code without having any debugger on. You should see the WDG overflow causing an SMU alarm, and the SMU alarm causing the reset. 

 

I hope this helps get you application running properly.

Good luck 🙂 

AMG_0-1651837356939.png

 

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jica-zhang
Level 3
Level 3
25 replies posted 10 questions asked 25 sign-ins

Hello, configure this specific alert to take the behavior you want: NMI, interrupts, etc..  Which register is this configured?  

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AMG
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When configuring the appropriate fields in Tresos, the code generated takes care of the registers. 

The registers configured are the SMU AGiCFj registers. Have a look at the TC3xx User Manual, SMU Chapter (see screenshot). 

AMG_0-1652081010965.png

 

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jica-zhang
Level 3
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Hello, as shown in the picture, after WDG times out, it sends the timeout signal to SMU. Is smU reset in the following two ways?  What if I want to trigger the timer0 count from path 2 and then reset via alm10[16]?  And is the timer0 count status register available?  

jicazhang_1-1652164803008.png

 

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Di_W
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Hi Jica,

By default, NMI will do nothing( as TRAPDIS0 is 0xFFFF FFFF ), and Recovery Timer0/1 will do timeout and trigger Reset. Attached is fyi.

dw_0-1652460430840.png

dw

 

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The following is the MCAL code configured with EB,Wdg_17_Scu_Init(&Wdg_17_Scu_Config_0) and IrqGtm_Init();  Void Wdg_17_Scu_Isr(const Uint8 LogicalChId, const uint32 IsrStatus) is unavailable when the program runs after initialization.  

jicazhang_1-1652680165795.png

 

jicazhang_0-1652679917327.png

 

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