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hanumanagowda
Level 1
Level 1
First reply posted First like given First question asked

Hello,

 

In  AURIX TC397 MCU,  the SCU Reset Control Unit configuration is done as per the below,

hanumanagowda_0-1670767524641.png

 

While the SW Reset request is triggered, the SCU Reset Control Unit configuration looks like,

hanumanagowda_1-1670767649194.png

and the ESR0CNT is configured as 0

hanumanagowda_2-1670767799017.png

Could you please help me on how can we check via registers the ESR0_port pin level changed from HIGH to LOW after SW reset is triggered.  also where to place breakpoint in software to see the ESR0 pin level change?

Note: we don't have the option to check pin level via oscilloscope as the board is vendor provided proprietary and it is a closed one.

 

Also from the pictures it is seen that ESR0_OUT register and ESR0_IN register has different values.

ESR0_OUT pin says low,

ESR0_IN pin says High

could you please clarify me which one is valid level on the ESR0_pin?

 

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2 Replies
Prudhvi
Moderator
Moderator
Moderator
50 solutions authored 250 sign-ins 10 likes given

Hello,

If the conditions mentioned in the section "3.1.1.7.8 ESR0 pin handling" of the UserManual  are satisfied, the SSW clears the ARI bit based on ESR0CNT configuration.

Please see sections "3.1.1.7.8 ESR0 pin handling" and "9.1.4.1 External Service Requests (ESRx)" in the UM for more details. I assume you've configured the ESR0 to function as both Input and Output hence the difference.
The ESR0_IN reflects the current state of the pin. Please see "Table 252 PC0 Coding" in the same chapter.

Regards,

Prudhvi.

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Hello,

Thanks for the answer.

ESR0 IOCR pin is configured as output. 

hanumanagowda_0-1670819482066.png

when SW Reset is triggered by setting bit SWRSTREQ in SCU_SWRSTCON register, the ESR0 pin level is unchanged (SCU_IN P0 is HIGH and SCU_OUT P0 is LOW ) and ARI bit in SCU_ESR0CFG is still LOW which should have been HIGH.

could you please suggest what could have been the issue?

 

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