AURIX™ Forum Discussions

[metehanaydin]

Hello All

I would like to configure QSPIx as slave. So I will have pins connected as follows

MTSRxA to H (MOSI A to H)__Data from Master Devices

SCLKxA to H _____________SPI Clock from Master devices

nSLSIxB to H(CS B to H)____Slave Chip Select from Master Devices

MRSTx (MISO)____________Data from Slave QSPIx

Now my questions:

1) Why we have A..H, in total 8 pins, SPI Slave CLK IN and  MTSR but only 7 nSLSI Chip Select pins ? How can I use all 8 SPI Slaves with 7 Chip Selects?

2) Is there a limit on simultaneous Masters enabled Chip Select at the same time ? For example, assume I configure QSPI1 as slave and connect SCLK1B, MTSR1B, nSLSI1B;  to Master Device1 and SCLK1C, MTSR1C, nSLSI1C to Master Device 2. Can they independently and simultaneously insert nSLSI1B and nSLSI1C ? Do they have dedicated FIFOs for B and C or are there any degradation on data receive bandwidth if they are somehow using same FIFO?

Bests

Metehan

[µC_Wrangler]

Hi Metehan.  Each QSPI peripheral supports only one instance of MTSR, MRST, and CLK.  It's a little easier to read in the variant-specific User's Manual: see Table 408  Connections of QSPI0 in TC39xB_appx_um_v2.0.pdf as an example.  Each QSPI peripheral has one receive FIFO and one transmit FIFO.

In other words: assuming the AURIX is a SPI slave, and there are multiple external master devices, for QSPI0:

- Bus the CLK traces together, and route them to one of SCLKA (P20.11: QSPI0_PISEL.SCIS=0), SCLKB (P22.8: QSPI0_PISEL.SCIS=1), or SCLKC (P22.7: QSPI0_PISEL.SCIS=2).

- Bus the MRST traces together, and route them to one of MRSTA (P20.12: QSPI0_PISEL.MRIS=0), MRSTB (P22.9: QSPI0_PISEL.MRIS=1), or SCLKC (P22.6: QSPI0_PISEL.MRIS=2).

- (extend for MTSR and SLSI)

But is that really what you're after?  It's far more typical to have the AURIX be the QSPI *master*, not the slave.  In that case, the AURIX can assert one chip select output per transfer, depending on QSPIx_BACON.CS, and QSPIx_SSOC.  As a SPI master, the AURIX then drives MTSR and CLK, and receives data from the slave on MRST.

[metehanaydin]

Hi @µC_Wrangler 

First of all thanks for your answer. It is required that I need to use Aurix as slave from System POV.

"Each QSPI peripheral supports only one instance of MTSR, MRST, and CLK"

So does it mean that I can not use both QSPI0_A and QSPI0_B simultaneously ?

QSPI0_SCLKA, QSPI0_MTSRA, SLSIA    for 1 Master device and

QSPI0_SCLKB,QSPI0_MTSRB,SLSIB for another Master Device ?

But from your example, I understand I can use simultaneously 3 different independent Master Device connected to QSPI0 configured as slave.

Thanks again

Metehan

[µC_Wrangler · Accepted solution]

Hi Metehan.  You cannot use QSPI0_A and QSPI0_B simultaneously.  The idea is that you can choose from a number of pins for each QSPI peripheral (QSPI0, QSPI1, etc.); but ultimately, only one set of pins.

For the scenario you describe with 3 external masters, and the AURIX SPI in slave mode, the SCLK input from the masters will be tied into a single AURIX pin.  The same goes for MTSR and select.  MRST will fan out from a single AURIX pin into each master's MRST.

If you want to support simultaneous transfer, you'll need to use separate QSPI peripherals for each master.  For example, QSPI0 for Master Device 1, QSPI1 for MD2, QSPI2 for MD3, etc.