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Songlin
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5 likes given 5 replies posted 25 sign-ins

hello everyone,

         I want to ask a question about OVC of TC397.

Setting Description: 

       I use multicore of TC397.The target adress is in PF4. The OVC redirection address is LMU(0xBxxxxxxx).The Cache(DCache and PCache) of each core is enable in startup. The OVC of each core is enable by core0. and each section is set by core0.DCINVAL is set to 1 by core 0. In a word, every setting about OVC is set by core0.

      Var_A is a const variable in my target adress and redirection adress is  LMU(0xBxxxxxxx),Var_B and Var_C are common variable. I use  XCP to change Var_A in core0, use (Var_B = Var_A) in core0, use (Var_C = Var_A) in core4.     

Error Description:

     Var_B is changed with Var_C,but Var_C is not and keep init value.

       Then I do some test,the result is that the DCache of core4 must be bypass,regardless the Dcache of  Core 0 is enable or bypass,  both Var_B and Var_C can be changed  with var_A. 

But in my project ,I must enable Dcache of each core to improve performance.

What can I do to make  OVC work in the situation of making DCache of each core enable.

thank you 

 

 

 

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1 Solution
Jeremy_Zhou
Moderator
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25 replies posted 25 sign-ins First solution authored

Hi @Songlin ,

Thank you for your interest in Infineon Semiconductor products and for the opportunity to serve you.
Could you please explain in more detail? Further, could you share your code to replicate the phenomenon?

BR,

Jeremy

View solution in original post

10 Replies
Jeremy_Zhou
Moderator
Moderator
Moderator
25 replies posted 25 sign-ins First solution authored

Hi @Songlin ,

Thank you for your interest in Infineon Semiconductor products and for the opportunity to serve you.
Could you please explain in more detail? Further, could you share your code to replicate the phenomenon?

BR,

Jeremy

Dear Jeremy_Zhou,

Thanks for your reply.

The code is in an encrypted state,I don't have access to decrypt it.

more detail

1.Dcache Set

   #define IFX_CFG_SSW_ENABLE_TRICOREx_DCACHE (1U)

    dcon0.B.DCBYP = IFX_CFG_SSW_ENABLE_TRICORE0_DCACHE ? 0 : 1;

    the setting is by each core in __Corex_start, so every core's DCache is enable.

 

2.Diable and enable ovc block

void IfxCpu_disableOverlayBlock(IfxCpu_ResourceCpu cpu, uint16 overlayBlock)

void IfxCpu_enableOverlayBlock(IfxCpu_ResourceCpu cpu, uint16 overlayBlock, IfxCpu_OverlayMemorySelect overlayMemorySelect, IfxCpu_OverlayAddressMask overlayAddressMask, uint32 targetBaseAddress, uint32 overlayBaseAddress)

these two function are in iLLD. the enable function is called by core0.

calibration pflash is 0x80CExxxxx(Cache),ovc ram is 0xB00Axxxx(NonCache), 64k.

I enable every core's  OVC .

3.Test

  Var_A is a const variable ,Var_B and Var_C are common variable. I use  XCP to change Var_A in core0,means write in core0. use (Var_B = Var_A) in core0 and use (Var_C = Var_A) in core4 , means read in core0 and core4.

4.result

   Var_B is changed with Var_A,but Var_C is not and keep init value. means read data in core0 is update,but in core4 is not.

   If I close the Dcache of core4, the date read both of core0 and core4 can be update.

Looking forward to reply.

Thanks.

 

 

void IfxCpu_enableOverlayBlock(IfxCpu_ResourceCpu cpu, uint16 overlayBlock, IfxCpu_OverlayMemorySelect overlayMemorySelect, IfxCpu_OverlayAddressMask overlayAddressMask, uint32 targetBaseAddress, uint32 overlayBaseAddress)
{
    Ifx_CPU *ovcSfrBase = NULL_PTR;
    switch (cpu)
    {
    case IfxCpu_ResourceCpu_1:
        ovcSfrBase = &MODULE_CPU1;
        break;
    case IfxCpu_ResourceCpu_2:
        ovcSfrBase = &MODULE_CPU2;
        break;
    case IfxCpu_ResourceCpu_3:
        ovcSfrBase = &MODULE_CPU3;
        break;
    case IfxCpu_ResourceCpu_4:
        ovcSfrBase = &MODULE_CPU4;
        break;
    case IfxCpu_ResourceCpu_5:
        ovcSfrBase = &MODULE_CPU5;
        break;
    default:
        ovcSfrBase = &MODULE_CPU0;
        break;
    }
    /* Select overlay Block */
    ovcSfrBase->OSEL.U |= 1 << overlayBlock;
    /* Configure ovcBlock */
    Ifx_CPU_BLK_RABR rabr;
    Ifx_CPU_BLK_OTAR otar;
    rabr.U                                = 0;
    rabr.B.OMEM                           = overlayMemorySelect;
    rabr.B.OBASE                          = overlayBaseAddress >> 5;
    otar.U                                = 0;
    otar.B.TBASE                          = targetBaseAddress >> 5;
    ovcSfrBase->BLK[overlayBlock].RABR.U  = rabr.U;
    ovcSfrBase->BLK[overlayBlock].OTAR.U  = otar.U;
    ovcSfrBase->BLK[overlayBlock].OMASK.U = ((overlayAddressMask << 5) & 0x0001FFE0);
    /* Enable Overlay in SCU */
    uint16         safetyWdtPw = IfxScuWdt_getSafetyWatchdogPassword();
    IfxScuWdt_clearSafetyEndinit(safetyWdtPw);
    Ifx_SCU_OVCCON ovccon;
    ovccon.U = MODULE_SCU.OVCCON.U;
    switch (cpu)
    {
    case IfxCpu_ResourceCpu_1:
        MODULE_SCU.OVCENABLE.B.OVEN1 = 1;
        ovccon.B.CSEL1               = 1;
        break;
    case IfxCpu_ResourceCpu_2:
        MODULE_SCU.OVCENABLE.B.OVEN2 = 1;
        ovccon.B.CSEL2               = 1;
        break;
    case IfxCpu_ResourceCpu_3:
        MODULE_SCU.OVCENABLE.B.OVEN3 = 1;
        ovccon.B.CSEL3               = 1;
        break;
    case IfxCpu_ResourceCpu_4:
        MODULE_SCU.OVCENABLE.B.OVEN4 = 1;
        ovccon.B.CSEL4               = 1;
        break;
    case IfxCpu_ResourceCpu_5:
        MODULE_SCU.OVCENABLE.B.OVEN5 = 1;
        ovccon.B.CSEL5               = 1;
        break;
    default:
        MODULE_SCU.OVCENABLE.B.OVEN0 = 1;
        ovccon.B.CSEL0               = 1;
        break;
    }
    ovccon.B.OVSTRT     = 1;
    MODULE_SCU.OVCCON.U = ovccon.U;
    IfxScuWdt_setSafetyEndinit(safetyWdtPw);
}
 
void IfxCpu_disableOverlayBlock(IfxCpu_ResourceCpu cpu, uint16 overlayBlock)
{
    Ifx_CPU          *ovcSfrBase = NULL_PTR;
    Ifx_SCU_OVCCON    ovccon;
    Ifx_SCU_OVCENABLE ovcenable;
    uint16            safetyWdtPw = IfxScuWdt_getSafetyWatchdogPassword();
    IfxScuWdt_clearSafetyEndinit(safetyWdtPw);
    ovccon.U    = MODULE_SCU.OVCCON.U;
    ovcenable.U = MODULE_SCU.OVCENABLE.U;
    /* Disable Overlay in SCU */
    switch (cpu)
    {
    case IfxCpu_ResourceCpu_1:
        ovcSfrBase        = &MODULE_CPU1;
        ovcenable.B.OVEN1 = 0;
        ovccon.B.CSEL1    = 0;
        break;
    case IfxCpu_ResourceCpu_2:
        ovcSfrBase        = &MODULE_CPU2;
        ovcenable.B.OVEN2 = 0;
        ovccon.B.CSEL2    = 0;
        break;
    case IfxCpu_ResourceCpu_3:
        ovcSfrBase        = &MODULE_CPU3;
        ovcenable.B.OVEN3 = 0;
        ovccon.B.CSEL3    = 0;
        break;
    case IfxCpu_ResourceCpu_4:
        ovcSfrBase        = &MODULE_CPU4;
        ovcenable.B.OVEN4 = 0;
        ovccon.B.CSEL4    = 0;
        break;
    case IfxCpu_ResourceCpu_5:
        ovcSfrBase        = &MODULE_CPU5;
        ovcenable.B.OVEN5 = 0;
        ovccon.B.CSEL5    = 0;
        break;
    default:
        ovcSfrBase        = &MODULE_CPU0;
        ovcenable.B.OVEN0 = 0;
        ovccon.B.CSEL0    = 0;
        break;
    }
    ovccon.B.OVSTP         = 1;
    ovccon.B.DCINVAL       = 1;
    MODULE_SCU.OVCCON.U    = ovccon.U;
    MODULE_SCU.OVCENABLE.U = ovcenable.U;
    IfxScuWdt_setSafetyEndinit(safetyWdtPw);
    ovcSfrBase->BLK[overlayBlock].RABR.U  = 0;
    ovcSfrBase->BLK[overlayBlock].OTAR.U  = 0;
    ovcSfrBase->BLK[overlayBlock].OMASK.U = 0;
}

 

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Jeremy_Zhou
Moderator
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Moderator
25 replies posted 25 sign-ins First solution authored

Hi @Songlin ,

I was wondering if you can create a simple code based on the iLLD demos, which can replicate the phenomenon, then I can run it on my site for further checking.

BR,

Jeremy

Dear Jeremy_Zhou,

i cant find the entry to post the project,could i send a email to you.

please tell me your email in message.

Looking forward to reply.

Thanks.

 

Looking forward to reply.

Thanks.

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Dear Jeremy_Zhou,

Here is  the project.

Looking forward to reply.

Thanks.

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Jeremy_Zhou
Moderator
Moderator
Moderator
25 replies posted 25 sign-ins First solution authored

Hi @Songlin ,

 After going through the code, I've some inquiries.
Firstly, I find that the overlay Base Address is 0xB00A0000, however, in the follow-up code, it seems like the Test_Algo_Updateincore0 array should be the overlay memory.
Next, I'm not clear with the below test description, do you mean to modify the values of the Test_Map_Cal_Flash via the IDE?

 

/******test Description*******
 * 1.flash elf by trace32,
 * 2.turnon the 'OVC' in Trace32,
 * 2.enableovc: enable all core's OVC;then Test_Map_Cal_Flash change to 0
 * 3.change Test_Map_Cal_Flash
 * 3.view Test_Algo_Updateincorex,only Test_Algo_Updateincore3 can be changed with Test_Map_Cal_Flash,because its Dcache disable
 * ***************************/

 


Lastly, I don't find the variables like var_A, var_B and var_C?

So can you please clarify them?

BR

Jeremy

Dear Jeremy_Zhou,

Thanks for your reply.

1.Test_Map_Cal_Flash arry is const and in Pflash,and the address of Test_Map_Cal_Flash is Target Address 0xB00A000 is the Base Address, the overlay size is 512byte.

2.when ovc is enable,I can change Test_Map_Cal_Flash by Trace32,just like calibration by xcp.

3.Test_Map_Cal_Flash is  var_A, Test_Algo_Updateincore0 is var_B and is the value  of Test_Map_Cal_Flash is  var_A is CPU0's point,Test_Algo_Updateincore3 is var_C and is the value  of Test_Map_Cal_Flash is  var_A is CPU3's point.

4.And I have another question:In OVC function,when the target address is cacheable(0x8xxxxxxxx),and the redirection address is noncacheable(0xBxxxxxxx),and Dcache of each CPU is enable. when the OVC is enable,  the CPU access to the varriable in target address, is by cache or noncache?

I find it seems that even the base address is noncache(0xBxxxxxxxx),when the target address is cache(0x8xxxxxxx), the access will keep cache.But I don't find any descripion in any docment,so I am not sure it is right or not.

Looking forward to your reply.

Thanks.

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Jeremy_Zhou
Moderator
Moderator
Moderator
25 replies posted 25 sign-ins First solution authored

Hi @Songlin ,

Thanks for your reply.
In my opinion, your question is nothing related to the OVC, because the overlay Base Address is 0xB00A0000, however, Test_Algo_Updateincore arrays are not resided in this area actually,

code.pngAccording to your statement, you use the IDE to modify the Test_Map_Cal_Flash's values, then use the modified values to set the Test_Algo_Updateincore arrays, some works well, and other fails, is my understanding right?
Further, I don't think the cache affects the OVC feature.
Lastly, I'd like to suggest you program the flash via the code instead of IDE, to eliminate the IDE's possible affection.

BR,

Jeremy

Hi Jeremy_Zhou,

Thans for your reply.

I think the real question is DCache Coherency in Tricore.

Test_Algo_Updateincorex are not the Calibration variable,so they are not need to redirection to the Base Address.Test_Map_Cal_Flash is the realy calibration variable.I just use (Test_Algo_Updateincorex=Test_Map_Cal_Flash) in each core to view Test_Map_Cal_Flash is changed or not in each CPU's point.

 

So I want to ask the question how to solve the Cache Coherency in tricore when I want to us DCache. And do you have any demo.

Looking forward to your reply.

Thanks.

 

 

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Jeremy_Zhou
Moderator
Moderator
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25 replies posted 25 sign-ins First solution authored

Hi @Songlin ,

Thanks for your reply.
Firstly, I'd like to suggest you refer to learn how to maintain the cache coherency by referring to the attachment.
Next, I think you'd better refer to the demo to modify the values in the flash instead of utilizing the IDE for further testing.
BR,

Jeremy