TC397 Eth Module Internal Mac Status

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Hello:

Because now I want to monitor the link status of TC397 internal MAC, so as to observe whether my Eth module is working properly, I found the two registers MAC_PHYIF_CONTROL_STATUS and MAC_LPI_CONTROL_STATUS, but when I power off the external phy chip, the two registers are not viewed to the I would like to know if there is any way to monitor them? I would like to know if there is a way to monitor this, or a way to satisfy my need.

Currently my project is using MCAL and then using the code generated from the EB configuration to implement the driver and application code related to the network module.

 

#TC397 #Eth

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Try the PLS and PLSEN bits of MAC_LPI_CONTROL_STATUS.

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I have tried PLSEN for MAC_LPI_CONTROL_STATUS and TC position 1 for MAC_PHYIF_CONTROL_STATUS with the code GETH_MAC_LPI_CONTROL_STATUS.B.PLSEN = 1; GETH_MAC_PHYIF_CONTROL _STATUS.B.TC = 1;

But when I look at the registers in debug, they are always 0 except for the TC bit and the PLSEN bit that I set myself, which change to 1

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When using the MII interface, the PHY must be configured using the Management Data Input/Output Interface (MDIO). There are dedicated read/write functions for this purpose.

When using the RGMII, SGMII, and SMII interfaces, the PHY must be configured directly through the media-independent interface between the MAC and the PHY, rather than through the MDIO.In this case, register MAC_PHYIF_CONTROL_STATUS provides information about the Link Status bit (LNKSTS).

See what type of interface you have?

Two common methods of PHY configuration: through the Management Data Input/Output Interface (MDIO) and directly through the Media Independent Interface.

  • MDIO Configuration Methods
    The first way to configure the PHY is to use the MDIO interface.The MDIO interface is implemented through two signals, the MDIO interface clock (MDC) and the MDIO data. The MDIO connection can be checked using the following read and write functions:

Read function example:

void IfxGeth_phy_Clause22_readMDIORegister(uint32 layerAddr, uint32 regAddr, uint32 *pData)
{
// 5位物理层地址、5位GMII寄存器编号、4位时钟分频器、读、忙
GETH_MAC_MDIO_ADDRESS.U = (layerAddr << 21) | (regAddr << 16) | (0 << 😎 | (3 << 2) | (1 << 0);

IFXGETH_PHY_WAIT_GMII_READY();

// 获取数据
*pData = GETH_MAC_MDIO_DATA.U;
}


Write function example:

void IfxGeth_Phy_Clause22_writeMDIORegister(uint32 layerAddr, uint32 regAddr, uint32 data)
{
// 放置数据
GETH_MAC_MDIO_DATA.U = data;

// 5位物理层地址、5位GMII寄存器编号、4位时钟分频器、写、忙
GETH_MAC_MDIO_ADDRESS.U = (layerAddr << 21) | (regAddr << 16) | (0 << 😎 | (1 << 2) | (1 << 0);

IFXGETH_PHY_WAIT_GMII_READY();
}


The implementation of these two functions can be found in the corresponding files of the AURIX project.

  • Media Independent Interface Configuration Methods
    The second method of configuring the PHY is directly through the media independent interface. This configuration method is only applicable to fast media independent interfaces such as RGMII, SGMII and SMII, because in these cases there is no physical connection between the MAC and the PHY via MDIO. In this case, we can get information about the Link Status bit (LNKSTS) via register MAC_PHYIF_CONTROL_STATUS.

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I have it configured in EB Tresos for the RGMII interface.

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Hello, I have a project using the illd library, but I found the same phenomenon, the two registers I mentioned above do not have corresponding values. And when I look at the registers with Lauterbach it looks like this

xiaoyang_code_0-1707098012994.png

 

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Confirmation of this program as well?

https://github.com/Infineon/AURIX_code_examples/tree/master/code_examples/Ethernet_1_KIT_TC397_TFT

 

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