Announcements

Help us improve the Power & Sensing Selection Guide. Share feedback

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
User22569
Level 1
Level 1
Hello all,
TC397 is used in my project.

I want enable LMU memory protection, but encountered some difficulties.

my thoughts:
1. LMU2 memory address at 0xb00c0000 + 32K by used TAG ID protected.
2. LMU2 start range 32Kbytes write enable except CPU0.
3. declare variables into this area.
4. testcase CPU0 write val, see result.

code example:

int32_t lmu_safety_init(const lmu_range_safety_t *lmu_range_array, const uint32_t array_length)
{
uint8_t i;
int32_t status = 0;

if (array_length > 16)
{
status = -1;
}
else
{
Ifx_LMU *lmu;
Ifx_LMU_CLC clc;

lmu = &MODULE_LMU2;
clc.U = lmu->CLC.U;
clc.B.DISR = 0;
Mcal_WriteSafetyEndInitProtReg(&lmu->CLC, clc.U);

for (i = 0; i < array_length; i++)
{
Mcal_WriteSafetyEndInitProtReg(&lmu->RGN.LA, lmu_range_array.start_addr & (IFX_LMU_RGN_LA_ADDR_MSK << IFX_LMU_RGN_LA_ADDR_OFF));
Mcal_WriteSafetyEndInitProtReg(&lmu->RGN.UA, lmu_range_array.end_addr & (IFX_LMU_RGN_UA_ADDR_MSK << IFX_LMU_RGN_UA_ADDR_OFF));
Mcal_WriteSafetyEndInitProtReg(&lmu->RGN.ACCENA, lmu_range_array.wenmask[0]);
Mcal_WriteSafetyEndInitProtReg(&lmu->RGN.ACCENB, lmu_range_array.wenmask[1]);
}
ISYNC();
DSYNC();
}

return status;
}

#pragma section "Lmusf.Unspecified" aw 4
static uint8_t lmutestdata[32*1024] = {0};
#pragma section

void lmu_safety_test(void)
{
int cpu_id;
int i;

cpu_id = cpu_id();

printf("CPU %d original lmusfdata:%u\n", cpu_id, lmutestdata[32 * 1024 - 1]);
for (i = 0; i < 32 * 1024; i++)
{
lmutestdata = cpu_id;
}
printf("CPU %d modified lmusfdata:%u\n", cpu_id, lmutestdata[32 * 1024 - 1]);
}

const lmu_range_safety_t lmu_safety_table[1] = {
{0xB00C0000U, 0xB00C0000U + (32 * 1024), {0xFFFFFFFFU, 0xFFFFFFFFU}, {0xFFFFFFF9U, 0xFFFFFFFFU}}
};

map file:
0xb00c0000 0xb00c7fff 32768 l lmutestdata lmuram_sfnc .lmuramsf lmusf.Unspecified drivers\lmu.o

step1:
lmu_safety_init(&lmu_safety_table[0], sizeof(lmu_safety_table) / sizeof(lmu_safety_table[0]));

step2: on other CPU1~5 call lmu_safety_test, change lmutestdata value;

also CPU0 call lmu_safety_test. but cpu0 as well as write lmutestdata sucessful.



why CPU0 disbale write , but write sucessful?
0 Likes
1 Solution
NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
That looks OK.

The protection is the permissive OR of all 16 ranges:
If overlapping regions are defined, then an access only needs to be permitted by one of the overlapping regions for it to succeed.


By default, the other 15 ranges allow access to the full LMU range by all bus masters. Try restricting the other 15 ranges (either ACCENW* or RGNLAx/RGNUAx) and let us know if there's still trouble.

View solution in original post

0 Likes
4 Replies
NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
Isn't your array_length loop just doing one iteration, where i=0? It looks to me like LMU2_RGNACCENWA0 and LMU_RGNACCENWB0 would both be 0xFFFFFFFF, which leaves access wide open. Please confirm the values you see at runtime in those two registers.
0 Likes
User22569
Level 1
Level 1
UC_wrangler wrote:
Isn't your array_length loop just doing one iteration, where i=0? It looks to me like LMU2_RGNACCENWA0 and LMU_RGNACCENWB0 would both be 0xFFFFFFFF, which leaves access wide open. Please confirm the values you see at runtime in those two registers.


LMU2_RGNACCENWA0 = 0xFFFFFFF9 and LMU_RGNACCENWB0 is 0xFFFFFFFF.
0 Likes
NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
That looks OK.

The protection is the permissive OR of all 16 ranges:
If overlapping regions are defined, then an access only needs to be permitted by one of the overlapping regions for it to succeed.


By default, the other 15 ranges allow access to the full LMU range by all bus masters. Try restricting the other 15 ranges (either ACCENW* or RGNLAx/RGNUAx) and let us know if there's still trouble.
0 Likes
User22569
Level 1
Level 1
UC_wrangler wrote:
That looks OK.

The protection is the permissive OR of all 16 ranges:


By default, the other 15 ranges allow access to the full LMU range by all bus masters. Try restricting the other 15 ranges (either ACCENW* or RGNLAx/RGNUAx) and let us know if there's still trouble.



The protection is the permissive OR of all 16 ranges:

thank you very much.!!!!
0 Likes