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User17486
Level 1
Level 1
This is my first time developing radar on AURIX.
I need to receive data from an analog board with microwave antennas (antenna module) with 4 quadrature channels (2 ADC lines per channel) and form a data cube for further processing.
The modulation is similar to FSK: aurix clocks the 25kHz antenna module, depending on the meander level, the antenna module sends data received at one of the two frequencies.
At each level of the clocking signal, it is necessary to organize a retreat on the transient PLL, make measurements for the remaining time, then average and record the only value of the data cube (total 2 values ​​for the period of the clocking signal).
Preferably, the data cube is organized in fifo, the second option is to collect 2048 pairs of samples (2048 periods of the clock signal).
Does anyone have any examples of configuring EVADC-Interrupt_router-RIF-Timer periphery?
To work with the radar chip RXS, there are good examples that helped to quickly understand the bundle registries-iLLD ideology. I would like something similar for analog antenna modules. I would appreciate any help
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4 Replies
NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
Hi SmileOn. The challenge here is that the RIF only supports the RXS and similar external ADCs.

You can get up to 2.4 MSPS out of the EVADC, but I'm guessing that for your application, you need to synchronize the converters so all 8 channels are read simultaneously.

One challenge is that on the TC397XA, you've only got 4 primary and 3 secondary converters available, from a glance at the datasheet - so you're one short of 8 channels.

Please discuss this further with an Infineon FAE or Preferred Design House partner to find an optimal solution.
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User17486
Level 1
Level 1
UC_wrangler wrote:
Hi SmileOn. The challenge here is that the RIF only supports the RXS and similar external ADCs.

Good day.
Let me disagree with you. In court for a user guide, the RIF supports external and internal ADCs. For external ADCs, LVDS is used.
In addition, the number of ADCs depends on the specific version of the package.
I found an application note for the XMC1200 VADC controller (Infineon-VADC-XMC1200_XMC1300-AP32304-AN-v01_10-EN.pdf), I find it similar to EVADC Tricore.
Unfortunately, application note specifically for EVADC Tricore I could not find in the documentation available to me.
I will follow your advice and appeal in support of infineon.
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NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
You're right about the RIF, but it only supports 4 internal ADCs.

The EVADC details are in the TC3xx User Manual (AURIXTC3XX_um_part2_V1.2.0.pdf). You can download it from MyICP once someone has granted TC3xx documentation access to your account.
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User17486
Level 1
Level 1
UC_wrangler wrote:
You're right about the RIF, but it only supports 4 internal ADCs.


I want to connect both RIFs (0 and 1) to SPU, then I’ll get 8 ADC lines. As I understand it is possible.

UC_wrangler wrote:


The EVADC details are in the TC3xx User Manual (AURIXTC3XX_um_part2_V1.2.0.pdf). You can download it from MyICP once someone has granted TC3xx documentation access to your account.


I have this document and I have been studying it for several days.
This is my first project on infineon. And my task is to create a non-trivial (in my opinion) input data algorithm.
Before that, I studied SPU and RIF with an RXS chip. Infineon has detailed examples and documentation for such solutions. But for the TIMER-IR-EVADC-RIF-SPU combination, I did not find a similar one.
I want to make using native tools, at a minimum use the CPU, but not sure whether it will work.
Ideally, I would like some appnote with a few user cases, or a project using iLLD, where aurix works with an analog radar module.
This would greatly accelerate the study, but I think that no one will give me that, so I will continue to understand myself.
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