AURIX™ Forum Discussions

[DownyK]

Hi everyone.

in Analog start-up, What is the state of the MCU in the event of PBIST2 failure?

As you can see in the figure above, PBIST2 is checking the OV, UV, of various voltages.

For example, if VDDP3 is OV, PBIST2 will fail, what is the state of the MCU?

Does it stop or reset?

Please Let me know.

Thanks

[cwunder]

This is described in the user manual chapter 11.2.2.5.1 and the device will not run until all the primary voltage levels are above their respective minimum thresholds.

[DownyK]

Thank you for your reply.

Let me be more precise. Is it the same if the issue occurs in the start-up sequence?

Looking at the above, it seems to be a description of the low voltage situation.

Is it the same in an overvoltage situation?

[cwunder]

Yes the primary monitors are always checking for under voltage and will assert the cold reset upon a violation.  Concerning the over voltage condition the AURIX can detect this but the reaction is up to the user.  It is assumed that the system detects and disables the supply rails to the AURIX when an over voltage condition occurs. Otherwise damage can occur to the AURIX depending on the voltage level applied to the respective power rail (see the datasheet). Typically the AURIX is paired with PMIC like the TLF35584. These devices have independent voltage monitoring of all output voltages. It can shut off the voltage supplies by going to a failsafe state (more information can be found in the datasheet of the TLF35584).

[DownyK]

Thank you for your reply.

I understand what you're saying.

However, what I'm still curious about is VDDP3 OV in the PBIST. As in the scenario, I showed you in the Question, it seems that the cold power on reset status is released only when the PBIST ends normally.

My conclusion is that if VDDP3 is OV at the time of PBIST, MCU seems to stay in a halt state.

I think what you said in the above comment is when an OV occurs in a situation where the SW rotates normally after PBIST.

[cwunder]

yes but you also need to be aware of this errata:

PMS_TC.007 VDDP3 or VDD Overvoltage during start-up may not be detected by PBIST

[DownyK]

The reason why I was asking is the Errata you mentioned. 

Errata said that PBIST does not detect OVs in VDDP3 and VDD.

Therefore, I thought that instead of PBIST,  SW should detect the OV of these voltages in advance and plan the action accordingly with SW.

However, as mentioned above, the original intention of PBIST is to halt the MCU during the OV of VDDP3 and VDD.

In the end, the original purpose is to halt MCU SW, but it is questionable how to deal with this SW.

If the SW detects the OV of VDDP3 and VDD, is there any possibility that the MCU will be damaged before that?

I am not finding the right answer to this.

thank you.