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I'm trying to figure out how the Cache Ram and Tag cache Ram is intended to work. (Program Cache TAG RAM, Data Cache TAG Ram, Data Cache ram etc). There is some reference?
These RAM section are automatically used by the uC or need to be explicitily "invoked" into the code/linker?
Cache Ram and cache Tag Ram are used automatically when the cache is switched on (default) and an access to any cached address occurs. There is nothing to define in linker script file for this memory. Please note that Cache Ram and Cache Tag Ram are not directly accessible by any CPU or debugger.
Thanks Mod for your reply. Where I can get some more information on when is better to use this features (cache/not cached) and when is better to avoid to use it? You wrote it is not diretly accessibly by the any CPU so who will use these ram section? S
You should always use the cache (increase execution speed). Therefore the cache is enabled per default. Using cache should be avoided for variable which are used by different CPUs or with DMA. Such variables should be places in non cached area. Not directly accessible by the CPU means that the CPU can't be access this memory via any address. If the cache is enabled then the CPU use this Rams but can't read directly the content via any address.
