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AURIX™ Forum Discussions

Anony
Level 2
Level 2
5 questions asked 10 replies posted 5 likes given
I'm debugging the Bootloader of TC375 and need to use flash driver. I found an official example《Flash_Programming_1_KIT_TC375_LK》. 
In the example demo , the flash write address is above 0xa000xxxx. I modify the write address to 0x8000xxx. When running flash write, a trap error will be sent.
When programming pflash, can't it be written with the address of 0x8000xxx? Or which function should be used when you need to write data at 0x8000xxxx address?
The following figure is the pflash write function:
 

1636624876.jpg

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1 Solution
cwunder
Employee
Employee
50 solutions authored 250 sign-ins 25 likes received

Command cycles shall address the non-cached address range of the Flash (otherwise the data may stay in the
cache or could be received by the DMU in an incorrect order).

Note: The memory is the same for cached (segment 8 ) and non-cached (segment A) of PFlash as there is only one physical memory. Only the way it is accessed by a Master changes. 

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cwunder
Employee
Employee
50 solutions authored 250 sign-ins 25 likes received

Command cycles shall address the non-cached address range of the Flash (otherwise the data may stay in the
cache or could be received by the DMU in an incorrect order).

Note: The memory is the same for cached (segment 8 ) and non-cached (segment A) of PFlash as there is only one physical memory. Only the way it is accessed by a Master changes. 

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Anony
Level 2
Level 2
5 questions asked 10 replies posted 5 likes given

Thank you very much for your answer. I'll try it.

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LijoDan
Level 2
Level 2
10 replies posted First question asked 10 likes given

I am trying to flash a TC377, the default location thats being flashed at the moment is 0xA0000000. But however there are some code being placed starting in 0x80000020 location. what is being placed here, are they are mirror of the actual Application hex in 0xA000 0000?

Anony
Level 2
Level 2
5 questions asked 10 replies posted 5 likes given

As cwunder said, the Pflash of cache segment and non cache segment is the same physical memory.

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