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Solved! Go to Solution.
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Aurix
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Command cycles shall address the non-cached address range of the Flash (otherwise the data may stay in the
cache or could be received by the DMU in an incorrect order).
Note: The memory is the same for cached (segment 8 ) and non-cached (segment A) of PFlash as there is only one physical memory. Only the way it is accessed by a Master changes.
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Command cycles shall address the non-cached address range of the Flash (otherwise the data may stay in the
cache or could be received by the DMU in an incorrect order).
Note: The memory is the same for cached (segment 8 ) and non-cached (segment A) of PFlash as there is only one physical memory. Only the way it is accessed by a Master changes.
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Thank you very much for your answer. I'll try it.
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I am trying to flash a TC377, the default location thats being flashed at the moment is 0xA0000000. But however there are some code being placed starting in 0x80000020 location. what is being placed here, are they are mirror of the actual Application hex in 0xA000 0000?
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As cwunder said, the Pflash of cache segment and non cache segment is the same physical memory.