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你好,

我有一些關於中斷的問題。

當中斷運行時,可以運行另一個更高優先順序的中斷嗎?

EVAL_6EDL7141_TRAP_1SH事件可以中斷該過程嗎?

有什麼可以中斷過程嗎?

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC375-interrupt-nesting/td-p/676525

1 解決方案
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@long

可以看出,回答你的問題時,除非是 NMI (如EVAL_6EDL7141_TRAP_1SH ),否則總是會出現較高的中斷,那麼,CPU 將服務較高的優先級直到最後,請檢查隨附的示例,並且如果需要根據您的需求進行修改,您也可以在MyICP上找到更多有關拱門的資訊。

問候!:1

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC375-interrupt-nesting/m-p/678766

在原始文章中檢視解決方案

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7 回應
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@long

關於您的問題:

1.-當中斷運行時,可以運行另一個更高優先順序的中斷嗎?

是的,確實您最多可以設置 256 個優先級別,更多信息可以在我們的基本培訓中斷路由器培訓中找到

2.- EVAL_6EDL7141_TRAP_1SH事件可以中斷該過程嗎?

是的, EVAL_6EDL7141_TRAP_1SH是由於不可屏蔽中斷 (NMI)、指令異常或非法存取等事件而發生的,有關它的更多資訊可以在TriCore™架構中找到,第 72 頁

3 .-有什麼可以中斷過程嗎?

好吧,這取決於,如果您的意思是還有什麼可以修改 MCU 程式的正常執行,它可能是:內部或外部中斷、 EVAL_6EDL7141_TRAP_1SH系統、看門狗計時器、錯誤編程(堆疊下溢/溢出) 、硬體/軟體重設、記憶體保護系統,SMU 發出兩次警報, TriCore™支援的領域之一是安全關鍵型嵌入式應用。該架構具有一個保護系統,旨在保護核心系統功能免受軟件錯誤的影響,因此我建議您查看我們的基本培訓並查看架構手冊,要訪問所有這些文件,請在 myICP 上註冊

問候!

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC375-interrupt-nesting/m-p/676954

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謝謝你的回复。

現在我已經嘗試在 TC375 中使用 ASCLIN 模塊,但很奇怪的是,即使在 RFL 和 TFL 標誌設置高時,RX ISR 還要等到 TX ISR 返回,也很奇怪

配置很大

Tx 中斷優先順序為 1。

Tx 中斷 TOS 為 cpu0。

Rx 中斷優先順序為 2。

Rx 中斷 TOS 為 cpu0。

組合了 FIFo 中斷模式。

 

 

 

 

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC375-interrupt-nesting/m-p/677422

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@long

您可以上傳代碼嗎,如果兩者看到相同的話,比較容易嘗試找到問題,

問候!

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC375-interrupt-nesting/m-p/677735

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@David_R

大部分程式碼可以在DEMO_5QR0680AG_42W1 “ASCLIN SPI Master 1 KIT_A2G_TC387_MOTORCTR TC375 LK”中找到。

環境是AURIX™開發工作室v1.9.20

我已經修改了其中的一些代碼,具體更改在插入的代碼中

 

 /* \file IfxAsclin_Spi.c*/
uint32 count_tx_fifo=0;
void IfxAsclin_Spi_write(IfxAsclin_Spi *asclin)
{
    Ifx_ASCLIN        *asclinSFR = asclin->asclin;    /* getting the pointer to ASCLIN registers from module handler */
    IfxAsclin_Spi_Job *job       = &asclin->txJob;    /* getting the txJob structure from module handler */

    if (job->pending)
    {
        //boolean interruptState = IfxCpu_disableInterrupts();

        uint32  count          = (uint32)(16 - IfxAsclin_getTxFifoFillLevel(asclinSFR)); /* getting the fillable count of the Tx Fifo */
        count_tx_fifo=count;
        count = __min(job->pending, count);                                              /* checking for the end of the data */
        //uint32 count=1;
        if (job->data == NULL_PTR)                                                       /* incase of no data to be transmitted (only receive case) */
        {
            uint32 i;
            job->pending = job->pending - count;                                         /* discount the current filling count from job pending */

            for (i = 0; i < count; i++)
            {
                IfxAsclin_writeTxData(asclinSFR, ~0); /* write all 1's */
            }
        }
        else
        {
            job->pending = job->pending - count;                      /* discount the current filling count from job pending */

            /* write data up to the count based on the in width */
//            switch (asclin->dataWidth)
//            {
//            case 1:                                             /* in case of 8 bit wide */
                IfxAsclin_write8(asclinSFR, job->data, count);  /* writing to Tx FIFO */
                job->data = &(((uint8 *)job->data)[count]);     /* pointing to the remaining data */
//                break;
//
//            case 2:                                             /* in case of 16 bit wide*/
//                IfxAsclin_write16(asclinSFR, job->data, count); /* writing to Tx FIFO */
//                job->data = &(((uint16 *)job->data)[count]);    /* pointing to the remaining data */
//                break;
//            }
        }

        //IfxCpu_restoreInterrupts(interruptState);
    }
}


void IfxAsclin_Spi_read(IfxAsclin_Spi *asclin)
{
    Ifx_ASCLIN        *asclinSFR = asclin->asclin;                                  /* getting the pointer to ASCLIN registers from module handler */
    IfxAsclin_Spi_Job *job       = &asclin->rxJob;                                  /* getting the rxJob structure from module handler */

    uint32             count     = (uint32)IfxAsclin_getRxFifoFillLevel(asclinSFR); /* get the readable count of Rx fifo */
    count = __min(job->pending, count);                                             /* check for the end of the data */
    //uint32 count=1;
    if (job->data == NULL_PTR)                                                      /* incase of no data to be received (only transmit case) */
    {
        uint32 i;
        job->pending = job->pending - count;                                        /* discount the current reading count from job pending */

        for (i = 0; i < count; i++)
        {
            IfxAsclin_readRxData(asclinSFR);    /* do dummy reads */
        }
    }
    else if (job->pending > 0)
    {
        job->pending = job->pending - count;    /* discount the current reading count from job pending */

        /* read data up to the count based on the out width */
//        switch (asclin->dataWidth)
//        {
//        case 1:                                            /* in case of 8 bit wide */
            IfxAsclin_read8(asclinSFR, job->data, count);  /* reading from Rx FIFO */
            job->data = &(((uint8 *)job->data)[count]);    /* pointing to the remaining data */
//            break;

//        case 2:                                            /* in case of 16 bit wide*/
//            IfxAsclin_read16(asclinSFR, job->data, count); /* reading from Rx FIFO */
//            job->data = &(((uint16 *)job->data)[count]);   /* pointing to the remaining data */
//            break;
//        }
    }

    if (job->pending == 0)
    {
        asclin->transferInProgress = 0; /* clearing the transfer in progress status */
        IfxAsclin_Spi_unlock(asclin);   /* unlock the driver  */
    }
}
void IfxAsclin_Spi_initModuleConfig(IfxAsclin_Spi_Config *config, Ifx_ASCLIN *asclin)
{
    const IfxAsclin_Spi_Config defaultConfig = {
        .asclin      = NULL_PTR,                           /* will be initialized below */

        .frameMode   = IfxAsclin_FrameMode_spi,            /* SPI mode */
        .clockSource = IfxAsclin_ClockSource_ascFastClock, /* Asclin fast clock, fasclinf*/

        /* Default values for input output control */
        .inputOutput              = {
            .alti     = IfxAsclin_RxInputSelect_0,               /* alternate input 0; */
            .cpol     = IfxAsclin_ClockPolarity_idleHigh,         /* CPOL  active low */
            .spol     = IfxAsclin_SlavePolarity_idlehigh,        /* SPOL  active high */
            .loopBack = FALSE,                                  /* no loop back */
        },

        /* Default Values for Bit sampling */
        .bitSampling              = {
            .medianFilter         = IfxAsclin_SamplesPerBit_one, /* one sample per bit */
        },

        /* Default Values for Frame Control */
        .frame                    = {
            .idleDelay = IfxAsclin_IdleDelay_0,                /* no idle delay */
            .leadDelay = IfxAsclin_LeadDelay_0,                /* one lead bit */
            .stopBit   = IfxAsclin_StopBit_0,                  /* one stop bit (trail delay) */
            .shiftDir  = IfxAsclin_ShiftDirection_msbFirst,    /* shift direction LSB first */
        },

        /* Default Values for Data Control*/
        .dataLength               = IfxAsclin_DataLength_8,          /* number of bits per transfer 8*/

        /* Default Values for fifo Control */
        .fifo                     = {
            .outWidth             = IfxAsclin_RxFifoOutletWidth_1,        /* 8-bit wide read */
            .inWidth              = IfxAsclin_TxFifoInletWidth_1,         /*8-bit wide write */
            .buffMode             = IfxAsclin_ReceiveBufferMode_rxFifo,   /* RxFIFO */
            .txFifoInterruptLevel = IfxAsclin_TxFifoInterruptLevel_0,    /* Tx FIFO interrupt level */
            .rxFifoInterruptLevel = IfxAsclin_RxFifoInterruptLevel_1,    /* Rx FIFO interrupt level */
            .txFifoInterruptMode  = IfxAsclin_FifoInterruptMode_combined, /* Tx FIFO interrupt generation mode */
            .rxFifoInterruptMode  = IfxAsclin_FifoInterruptMode_combined, /* Rx FIFO interrupt generation mode */
        },

        /* Default Values for Interrupt Config */
        .interrupt                = {
            .rxPriority    = 0,                            /* receive interrupt priority 0 */
            .txPriority    = 0,                            /* transmit interrupt priority 0 */
            .erPriority    = 0,                            /* error interrupt priority 0 */
            .typeOfService = IfxSrc_Tos_cpu0,              /* type of service CPU0 */
        },

        .pins                     = NULL_PTR,              /* pins to null pointer */
    };

    /* Default Configuration */
    *config        = defaultConfig;
    /* take over module pointer */
    config->asclin = asclin;
}
 /********************** file Cpu0_Main.c***********************/
#include "Ifx_Types.h"
#include "IfxCpu.h"
#include "IfxScuWdt.h"
#include "IfxScuCcu.h"
#include "ASCLIN1_SPI_Master.h"
IFX_ALIGN(4) IfxCpu_syncEvent g_cpuSyncEvent = 0;

float32 fre_asclin;

uint8 tx_data[2048] = {0x00};//1K*1024= 1M
uint8 rx_data[2048] = {0};

void core0_main(void)
{
    IfxCpu_enableInterrupts();

    /* !!WATCHDOG0 AND SAFETY WATCHDOG ARE DISABLED HERE!!
     * Enable the watchdogs and service them periodically if it is required
     */
    IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword());
    IfxScuWdt_disableSafetyWatchdog(IfxScuWdt_getSafetyWatchdogPassword());
    /* Wait for CPU sync event */
    IfxCpu_emitEvent(&g_cpuSyncEvent);
    IfxCpu_waitEvent(&g_cpuSyncEvent, 1);

    /* Initialize ASCLIN module in SPI master mode and transfer data  */
    InitAsclin1SpiMaster();

    for(uint16 i=0 ; i

 

 

 

 

 

 

 

 

 

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC375-interrupt-nesting/m-p/677953

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你好 @long

我附上了一個範例,演示優先順序如何運作以及任務如何被另一個任務搶佔,我使用了TC375 PSOC4_HVPA_LITE_KIT KIT_A2G_TC387_MOTORCTR

它是如何工作的:

在文件中 gpt12.c 您可以修改 T2 和 T4 的優先順序

#define T4_INT_NUM              (TX_INT_NUM - 1)
#define T2_INT_NUM              (T4_INT_NUM)

第一種情況都具有相同的優先順序,在終端上你應該看到這個輸出:

David_R_0-1705511552084.png

T4 和 T2 的優先順序相同,這就是為什麼 T2 沒有提供服務的原因(飢餓)

現在你更改 T2 的優先順序

#define T2_INT_NUM              (T4_INT_NUM - 1)

輸出將是:

 

David_R_2-1705511721809.png

所以 T4 比 T2 優先,這就是首先完成 T4 的原因

最後提高 T2 的優先順序:

#define T2_INT_NUM              (T4_INT_NUM + 1)

輸出將是

David_R_3-1705512006314.png

因此,現在 T2 優先於 T4,這就是為什麼 T2 比 T4 排名第一。

關於您的代碼,我真的建議在任何情況下,不要修改 Infineon 提供的庫的源代碼,您的代碼的可移植性將為空,也無需這樣做,最好製作更高的層,然後在那裡修改行為。

歡呼:1!

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC375-interrupt-nesting/m-p/678514

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@David_R

我想我已經知道中斷仲裁,確實如果TriCore™進入中斷並且另一個更高優先級的中斷請求進來,第一個中斷會繼續嗎?

 

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC375-interrupt-nesting/m-p/678667

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@long

可以看出,回答你的問題時,除非是 NMI (如EVAL_6EDL7141_TRAP_1SH ),否則總是會出現較高的中斷,那麼,CPU 將服務較高的優先級直到最後,請檢查隨附的示例,並且如果需要根據您的需求進行修改,您也可以在MyICP上找到更多有關拱門的資訊。

問候!:1

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC375-interrupt-nesting/m-p/678766

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