TC375 中断嵌套

公告

大中华汽车电子生态圈社区并入开发者社区- 更多资讯点击此

Tip / 登入 to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
Translation_Bot
Community Manager
Community Manager
Community Manager

你好,

我对中断有一些疑问。

当中断运行时,另一个更高优先级的中断能否运行?

EVAL_6EDL7141_TRAP_1SH事件会中断该过程吗?

有什么可以中断过程的吗?

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC375-interrupt-nesting/td-p/676525

0 点赞
1 解答
Translation_Bot
Community Manager
Community Manager
Community Manager

@long

可以看出,在回答您的问题时,除非是 NMI(如 EVAL_6EDL7141_TRAP_1SH),否则始终会参加较高的中断,因此,CPU 将提供更高的优先级直到最后,请查看随附的示例,如果需要根据您的需要进行修改,您还可以在 MyICP 上找到有关 arch 的更多信息。

问候!:1

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC375-interrupt-nesting/m-p/678766

在原帖中查看解决方案

0 点赞
7 回复数
Translation_Bot
Community Manager
Community Manager
Community Manager

@long

关于你的问题:

1.-当中断运行时,另一个更高优先级的中断能否运行?

是的,实际上你可以配置多达 256 个优先级,可以在我们的基本培训中断路由器培训中找到更多信息

2.- EVAL_6EDL7141_TRAP_1SH事件会中断该过程吗?

是的,EVAL_6EDL7141_TRAP_1SH是由于不可屏蔽中断 (NMI)、指令异常或非法访问等事件而发生的,有关它的更多信息可以在 TriCore™ 架构中找到,第 72 页

3. - 有什么可以中断过程的吗?

这取决于,如果你的意思是还有什么可以修改MCU程序的正常执行,它可能是:内部或外部中断、 EVAL_6EDL7141_TRAP_1SH 系统、看门狗定时器、错误编程(堆栈下溢/溢出)、硬件/软件复位、内存保护系统、SMU启动警报两次, TriCore™ 支持的领域之一是安全关键型嵌入式应用。 该架构具有保护系统,旨在保护核心系统功能免受软件错误的影响,因此我建议您查看我们的基础培训并查看架构手册,要访问所有这些文档,请在myICP 上注册

问候!

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC375-interrupt-nesting/m-p/676954

0 点赞
Translation_Bot
Community Manager
Community Manager
Community Manager

谢谢你的回复。

现在我已经尝试在 TC375 中使用 ASCLIN 模块了,但奇怪的是,即使 RFL 和 TFL 标志设置为高时 RX 优先级更高,Rx ISR 也要等到 TX ISR 返回

配置不对劲了

Tx 中断优先级为 1。

Tx 中断 TOS 是 cpu0。

Rx 中断优先级为 2。

Rx 中断 TOS 是 cpu0。

FiFo 中断模式是组合的。

 

 

 

 

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC375-interrupt-nesting/m-p/677422

0 点赞
Translation_Bot
Community Manager
Community Manager
Community Manager

@long

你能上传代码吗,如果两者看到的相同,尝试找到问题会更容易,

问候!

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC375-interrupt-nesting/m-p/677735

0 点赞
Translation_Bot
Community Manager
Community Manager
Community Manager

你好 @David_R

DEMO_5QR0680AG_42W1大部分代码可以在“ASCLIN SPI Master 1KIT_A2G_TC387_MOTORCTR TC375 LK” 中找到。

环境是开发工作室 v1.9.20 AURIX™

我已经修改了其中的一些代码,具体的更改在插入的代码中

 

 /* \file IfxAsclin_Spi.c*/
uint32 count_tx_fifo=0;
void IfxAsclin_Spi_write(IfxAsclin_Spi *asclin)
{
    Ifx_ASCLIN        *asclinSFR = asclin->asclin;    /* getting the pointer to ASCLIN registers from module handler */
    IfxAsclin_Spi_Job *job       = &asclin->txJob;    /* getting the txJob structure from module handler */

    if (job->pending)
    {
        //boolean interruptState = IfxCpu_disableInterrupts();

        uint32  count          = (uint32)(16 - IfxAsclin_getTxFifoFillLevel(asclinSFR)); /* getting the fillable count of the Tx Fifo */
        count_tx_fifo=count;
        count = __min(job->pending, count);                                              /* checking for the end of the data */
        //uint32 count=1;
        if (job->data == NULL_PTR)                                                       /* incase of no data to be transmitted (only receive case) */
        {
            uint32 i;
            job->pending = job->pending - count;                                         /* discount the current filling count from job pending */

            for (i = 0; i < count; i++)
            {
                IfxAsclin_writeTxData(asclinSFR, ~0); /* write all 1's */
            }
        }
        else
        {
            job->pending = job->pending - count;                      /* discount the current filling count from job pending */

            /* write data up to the count based on the in width */
//            switch (asclin->dataWidth)
//            {
//            case 1:                                             /* in case of 8 bit wide */
                IfxAsclin_write8(asclinSFR, job->data, count);  /* writing to Tx FIFO */
                job->data = &(((uint8 *)job->data)[count]);     /* pointing to the remaining data */
//                break;
//
//            case 2:                                             /* in case of 16 bit wide*/
//                IfxAsclin_write16(asclinSFR, job->data, count); /* writing to Tx FIFO */
//                job->data = &(((uint16 *)job->data)[count]);    /* pointing to the remaining data */
//                break;
//            }
        }

        //IfxCpu_restoreInterrupts(interruptState);
    }
}


void IfxAsclin_Spi_read(IfxAsclin_Spi *asclin)
{
    Ifx_ASCLIN        *asclinSFR = asclin->asclin;                                  /* getting the pointer to ASCLIN registers from module handler */
    IfxAsclin_Spi_Job *job       = &asclin->rxJob;                                  /* getting the rxJob structure from module handler */

    uint32             count     = (uint32)IfxAsclin_getRxFifoFillLevel(asclinSFR); /* get the readable count of Rx fifo */
    count = __min(job->pending, count);                                             /* check for the end of the data */
    //uint32 count=1;
    if (job->data == NULL_PTR)                                                      /* incase of no data to be received (only transmit case) */
    {
        uint32 i;
        job->pending = job->pending - count;                                        /* discount the current reading count from job pending */

        for (i = 0; i < count; i++)
        {
            IfxAsclin_readRxData(asclinSFR);    /* do dummy reads */
        }
    }
    else if (job->pending > 0)
    {
        job->pending = job->pending - count;    /* discount the current reading count from job pending */

        /* read data up to the count based on the out width */
//        switch (asclin->dataWidth)
//        {
//        case 1:                                            /* in case of 8 bit wide */
            IfxAsclin_read8(asclinSFR, job->data, count);  /* reading from Rx FIFO */
            job->data = &(((uint8 *)job->data)[count]);    /* pointing to the remaining data */
//            break;

//        case 2:                                            /* in case of 16 bit wide*/
//            IfxAsclin_read16(asclinSFR, job->data, count); /* reading from Rx FIFO */
//            job->data = &(((uint16 *)job->data)[count]);   /* pointing to the remaining data */
//            break;
//        }
    }

    if (job->pending == 0)
    {
        asclin->transferInProgress = 0; /* clearing the transfer in progress status */
        IfxAsclin_Spi_unlock(asclin);   /* unlock the driver  */
    }
}
void IfxAsclin_Spi_initModuleConfig(IfxAsclin_Spi_Config *config, Ifx_ASCLIN *asclin)
{
    const IfxAsclin_Spi_Config defaultConfig = {
        .asclin      = NULL_PTR,                           /* will be initialized below */

        .frameMode   = IfxAsclin_FrameMode_spi,            /* SPI mode */
        .clockSource = IfxAsclin_ClockSource_ascFastClock, /* Asclin fast clock, fasclinf*/

        /* Default values for input output control */
        .inputOutput              = {
            .alti     = IfxAsclin_RxInputSelect_0,               /* alternate input 0; */
            .cpol     = IfxAsclin_ClockPolarity_idleHigh,         /* CPOL  active low */
            .spol     = IfxAsclin_SlavePolarity_idlehigh,        /* SPOL  active high */
            .loopBack = FALSE,                                  /* no loop back */
        },

        /* Default Values for Bit sampling */
        .bitSampling              = {
            .medianFilter         = IfxAsclin_SamplesPerBit_one, /* one sample per bit */
        },

        /* Default Values for Frame Control */
        .frame                    = {
            .idleDelay = IfxAsclin_IdleDelay_0,                /* no idle delay */
            .leadDelay = IfxAsclin_LeadDelay_0,                /* one lead bit */
            .stopBit   = IfxAsclin_StopBit_0,                  /* one stop bit (trail delay) */
            .shiftDir  = IfxAsclin_ShiftDirection_msbFirst,    /* shift direction LSB first */
        },

        /* Default Values for Data Control*/
        .dataLength               = IfxAsclin_DataLength_8,          /* number of bits per transfer 8*/

        /* Default Values for fifo Control */
        .fifo                     = {
            .outWidth             = IfxAsclin_RxFifoOutletWidth_1,        /* 8-bit wide read */
            .inWidth              = IfxAsclin_TxFifoInletWidth_1,         /*8-bit wide write */
            .buffMode             = IfxAsclin_ReceiveBufferMode_rxFifo,   /* RxFIFO */
            .txFifoInterruptLevel = IfxAsclin_TxFifoInterruptLevel_0,    /* Tx FIFO interrupt level */
            .rxFifoInterruptLevel = IfxAsclin_RxFifoInterruptLevel_1,    /* Rx FIFO interrupt level */
            .txFifoInterruptMode  = IfxAsclin_FifoInterruptMode_combined, /* Tx FIFO interrupt generation mode */
            .rxFifoInterruptMode  = IfxAsclin_FifoInterruptMode_combined, /* Rx FIFO interrupt generation mode */
        },

        /* Default Values for Interrupt Config */
        .interrupt                = {
            .rxPriority    = 0,                            /* receive interrupt priority 0 */
            .txPriority    = 0,                            /* transmit interrupt priority 0 */
            .erPriority    = 0,                            /* error interrupt priority 0 */
            .typeOfService = IfxSrc_Tos_cpu0,              /* type of service CPU0 */
        },

        .pins                     = NULL_PTR,              /* pins to null pointer */
    };

    /* Default Configuration */
    *config        = defaultConfig;
    /* take over module pointer */
    config->asclin = asclin;
}
 /********************** file Cpu0_Main.c***********************/
#include "Ifx_Types.h"
#include "IfxCpu.h"
#include "IfxScuWdt.h"
#include "IfxScuCcu.h"
#include "ASCLIN1_SPI_Master.h"
IFX_ALIGN(4) IfxCpu_syncEvent g_cpuSyncEvent = 0;

float32 fre_asclin;

uint8 tx_data[2048] = {0x00};//1K*1024= 1M
uint8 rx_data[2048] = {0};

void core0_main(void)
{
    IfxCpu_enableInterrupts();

    /* !!WATCHDOG0 AND SAFETY WATCHDOG ARE DISABLED HERE!!
     * Enable the watchdogs and service them periodically if it is required
     */
    IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword());
    IfxScuWdt_disableSafetyWatchdog(IfxScuWdt_getSafetyWatchdogPassword());
    /* Wait for CPU sync event */
    IfxCpu_emitEvent(&g_cpuSyncEvent);
    IfxCpu_waitEvent(&g_cpuSyncEvent, 1);

    /* Initialize ASCLIN module in SPI master mode and transfer data  */
    InitAsclin1SpiMaster();

    for(uint16 i=0 ; i

 

 

 

 

 

 

 

 

 

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC375-interrupt-nesting/m-p/677953

0 点赞
lock attach
Attachments are accessible only for community members.
Translation_Bot
Community Manager
Community Manager
Community Manager

你好 @long

我附上了一个示例,演示了优先级的工作原理以及一个任务如何被另一个任务抢占,我使用了 TC375 PSOC4_HVPA_LITE_KIT KIT_A2G_TC387_MOTORCTR 

它是如何运作的:

在文件中 gpt12.c 你可以修改 T2 和 T4 的优先级

#define T4_INT_NUM              (TX_INT_NUM - 1)
#define T2_INT_NUM              (T4_INT_NUM)

第一种情况都具有相同的优先级,在终端上您应该看到以下输出:

David_R_0-1705511552084.png

T4 和 T2 的优先级相同,这就是 T2 没有发球(挨饿)的原因

现在你改变了 T2 的优先级

#define T2_INT_NUM              (T4_INT_NUM - 1)

输出将是:

 

David_R_2-1705511721809.png

所以 T4 优先于 T2,这就是为什么先完成 T4

最后提高 T2 的优先级:

#define T2_INT_NUM              (T4_INT_NUM + 1)

输出将是

David_R_3-1705512006314.png

所以现在 T2 比 T4 更有优先权这就是为什么 T2 比 T4 先完成的原因,

关于你的代码,我真的建议在任何情况下都不要修改英飞凌提供的库的源代码,你的代码的可移植性将为空,也没有必要这样做,最好做一个更高的层然后修改那里的行为。

干杯:1!

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC375-interrupt-nesting/m-p/678514

0 点赞
Translation_Bot
Community Manager
Community Manager
Community Manager

你好 @David_R

我想我已经知道中断仲裁了,确实如果 TriCore™ 进入一个中断,而另一个更高优先级的中断请求进来,第一个中断会继续吗?

 

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC375-interrupt-nesting/m-p/678667

0 点赞
Translation_Bot
Community Manager
Community Manager
Community Manager

@long

可以看出,在回答您的问题时,除非是 NMI(如 EVAL_6EDL7141_TRAP_1SH),否则始终会参加较高的中断,因此,CPU 将提供更高的优先级直到最后,请查看随附的示例,如果需要根据您的需要进行修改,您还可以在 MyICP 上找到有关 arch 的更多信息。

问候!:1

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/AURIX/TC375-interrupt-nesting/m-p/678766

0 点赞