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auftrag2022
Level 2
Level 2
25 sign-ins First solution authored First reply posted

Hello, 

we are using TC364DP for automotive application, when I was evaluating our test result for the GPIO logic (HI/LO) level), I found something very odd. 

According to the datasheet TC364DP, the high logic level is 0.7*VEXT for the "minimun", in our case, the VEXT is 5V, that means the threshold should be 3.5V as minimum. But I tested some many times (by low, room, high temperature), the threshold is only around 3.0V. It doesn't match the datasheet at all.

The low logic threshold is somehow matched to the datasheet.  (test value around 2.3V)

That means, the hysterisis windows for the GPIO (for automotive configuration) is not 0.44*VEXT to 0.7*VEXT but 0.44VEXT to 0.6*EXT. 

It caused a huge confusion for our application. Can some here help to approve this issue from Infineon side? Our HW requirement is quite high due to ASILD. I need to get very clear, what is really the worst case of the GPIO HIGH/LOW logic threshold.

auftrag2022_0-1666248173126.png

 

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1 Solution
Nambi
Moderator
Moderator
Moderator
5 likes given 100 solutions authored 250 replies posted

Hi,

The interpretation of VIH and VIL is as below.

i) any voltage above VIH will be reliably detected as a HIGH.
ii) any voltage below VIL will be reliably detected as a LOW.

So,

i) To detect a HIGH reliably at the input, you need to drive the input above 0.7*VEXT
ii) To detect a LOW reliably at the input, you need to drive the input below 0.44*VEXT

3.0V is between VIH and VIL. So, the input logic level cannot be reliably detected in this case.

Best Regards.

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4 Replies
Nambi
Moderator
Moderator
Moderator
5 likes given 100 solutions authored 250 replies posted

Hi,

Could you confirm the following?

i) Is any voltage above VIH reliably detected as a HIGH?
ii) Is any voltage below VIL reliably detected as a LOW?

Best Regards.

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for rising edge, if Vin > 3.0V, it will be recognized as "high"

for falling edge, if Vin < 2.3V, it will be recoginzed as "low"

my question is, what is the 0.7*VEXT supposed to mean?

auftrag2022_0-1666364535030.png

 

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Nambi
Moderator
Moderator
Moderator
5 likes given 100 solutions authored 250 replies posted

Hi,

The interpretation of VIH and VIL is as below.

i) any voltage above VIH will be reliably detected as a HIGH.
ii) any voltage below VIL will be reliably detected as a LOW.

So,

i) To detect a HIGH reliably at the input, you need to drive the input above 0.7*VEXT
ii) To detect a LOW reliably at the input, you need to drive the input below 0.44*VEXT

3.0V is between VIH and VIL. So, the input logic level cannot be reliably detected in this case.

Best Regards.

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auftrag2022
Level 2
Level 2
25 sign-ins First solution authored First reply posted

okay, thank you for clarifying. 

I think in this case we cannot take the measured 3.0V as a reliable "high" voltage, but must restrictively follow the 0.7*VEXT (around 3.5V) as the minimum for the high voltage detection as WORST CASE.

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