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AURIX™ Forum Discussions

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Dear Infineon forum members,
I am quite new in the forum and I would like to clarify the following concept which is not absolutely clear to me.
According to TC29xT block diagram, :http://www.infineon.com/export/sites/default/media/products/Microcontrollers/32bit/TC29xT_Block_Diag..., this microcontroller has 3 triCores (1lockstep). Does this mean 9 cores then?
I am a bit confused about how many cores are available so that different applications can be executed at the same time.

Thanks a lot.
Best regards,
Garazi
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µC_Wrangler
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100 sign-ins 25 likes received 25 solutions authored
The TC29x has three available cores.

This excerpt from TriCore Architecture Manual Vol1 explains the term TriCore:
The TriCore Instruction Set Architecture (ISA) combines the real-time capability of a microcontroller, the computational power of a DSP, and the high performance/price features of a RISC load/store architecture, in a compact re-programmable core.


This excerpt from the AURIX Safety Manual explains lockstep core operation:
A lockstep CPU detects permanent and transient faults in the CPU by the way of hardware redundancy, using two independent CPU instances called the master CPU and the checker CPU. The two CPUs operate in a lockstep manner: They use the same input data, execute the same operation, and all the functional outputs of the master cpu and the checker CPU are compared on a cycle basis by an hardware comparator.
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Hello Neal,

First of all, thanks a lot for your response.
My question mainly arises in terms of hardware capabilities for software parallelization into differente cores at the same ECU.
I would like to know how many resources/core are free denpending on the implementation. That's why I am trying to figure out the quantity of CPU/cores of the whole architecture.

If I have correctly understood, you mean that the Aurix TC29xT MC has 3 CPU with one single core each (3 task can be run in parallel). Regarding available memories, it consists of 1 RAM, 1 FLASH. Is that correct?


I thought that AurixTC29xT is based on multi-cpu, multi-core architecture http://stackoverflow.com/questions/680684/multi-
cpu-multi-core-and-hyper-threadhttp://
: 3 Tricore (3 independent CPU with multicore structure on each of it), being the lockstep CPU based on 3 cores for lockstep purpose.

If this would not be the case and an application is needed to be run as lockstep, it´s not clear to me how to deal with that. I have informed myself in different sources and different approaches seem to be chosen for this implementation:
- Option 1: Lockstep core and an additional core a needed for checking (CPU0 and CPU1 are occupied).
- Option 2: Only lockstep core is occupied running the application task (CPU0 occupied. CPU1 and CPU2 free).

In few words, with this Aurix architecture 3 tasks can be run in parallel, having the possibility to run one of them as lockstep.

Sorry for my possible misunderstanding and I hope I was clear enough. I would appreciate if you could clarify me this concept.

Thanks a lot.
Garazi
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µC_Wrangler
Employee
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100 sign-ins 25 likes received 25 solutions authored
Garazi wrote:
If I have correctly understood, you mean that the Aurix TC29xT MC has 3 CPU with one single core each (3 task can be run in parallel). Is that correct?
Mostly correct - except that CPU1 also has a lockstep core. That's part of the safety concept, and there's no impact on performance.

Garazi wrote:
Regarding available memories, it consists of 1 RAM, 1 FLASH.
Conceptually true, but the TC29x is a little more complicated - refer to the TC29x Block Diagram in the User Manual (1.2.1). Each core has its own local data RAM (DSPR) and program RAM (PSPR). There's also a shared 32K RAM (LMU), 8 MB of flash, and data flash. It's important to minimize the use of shared buses to achieve maximum performance.

Garazi wrote:
I thought that AurixTC29xT is based on multi-cpu, multi-core architecture http://stackoverflow.com/questions/680684/multi-
cpu-multi-core-and-hyper-threadhttp://
: 3 Tricore (3 independent CPU with multicore structure on each of it), being the lockstep CPU based on 3 cores for lockstep purpose.
The AURIX architecture does not include hyperthreading. For the TC29x, there are three CPU cores, one of which has a lockstep core.

Garazi wrote:
If this would not be the case and an application is needed to be run as lockstep, it´s not clear to me how to deal with that. I have informed myself in different sources and different approaches seem to be chosen for this implementation:
- Option 1: Lockstep core and an additional core a needed for checking (CPU0 and CPU1 are occupied).
- Option 2: Only lockstep core is occupied running the application task (CPU0 occupied. CPU1 and CPU2 free).
In few words, with this Aurix architecture 3 tasks can be run in parallel, having the possibility to run one of them as lockstep.

For the TC29x, the lockstep core is tied to CPU1. Partitioning the application so that safety critical tasks run on CPU1 with lockstep is often a challenge. Note that the TC27x includes a lockstep on one of the two performance cores (TC1.6P), and another on the efficiency core (TC1.6E).
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