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User17905
Level 1
Level 1
Hi there,
I'm trying to have run control with our own jtag controller but experiencing some issues.
I have a TC29x eval board and it has some pre-programmed flash that blinks LEDs. I'm able to halt and run (through trigger lines) the program in the flash. However, when I load my own dummy code which just toggle a variable in an infinite loop to CPU0.PSPR, after changing PC and let it run, code was not executed (I verified the data registers was not updated), and PC ends up at a wrong location in flash (0x80011fd4).
It seems there might be some security features being triggered.
I checked all watchdog timers, and they are all disabled.


Another question is regarding halt after reset feature. I was able to have it work. I see TCCH returns all CPUs are halted. PC is at 0xa0000020. But I was having trouble resume CPU0. The run control that's working is routing CPU0 to TL1 and CPU1 CPU2 to TL2. Resume CPU0 only would be working just by clearing TL1 capture and hold.
But in the case of halt after reset, TL2 is the default for CPU0 and TL2 status is read active. But I wasn't able to resume CPU0 by clearing TL2 capture and hold. What's the proper way to run CPU0 only in case of halt after reset?

Any suggestions and help would be much appreciated.

edit: I was able to see TL2 active after halt on reset, but still unable to run CPU0.

First question was resolved.

KJ
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3 Replies
ScottW
Employee
Employee
10 sign-ins First solution authored First like received
What is the state of the RSTSTAT register in each case? Depending on the board you're using, you may be running into an external watchdog issue:

https://www.infineonforums.com/threads/10334-New-code-does-not-run-on-Application-%28TFT%29-Kit?p=23...
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User17905
Level 1
Level 1
Thank you for the reply.
For power-on reset, RSTSTAT is 0x13810000. and for the system reset with halt after reset, RSTSTAT is 0x13850000.
I'm using triboard TC2x7.
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RValascho
Employee
Employee
First like received 5 questions asked First question asked
Hi KJ,

Address 0xA000020 is the start address of all TC2xx processors when the start mode is set to "Internal Start from Flash". This start mode is either set by HWCFG pins (P14.3 -> LOW, P10.5 -> HIGH, P10.6-> HIGH), or by a boot mode header. Look at "Startup Mode Selection Flow" in the manual. If boot mode header is applied, then there is an expected valid boot mode header at 1 of 4 locations ("Boot Mode Header Locations" in manual). In many cases the first halt case of the debugger will set the address correctly to 0xA0000020, but after reset the boot mode header is evaluated. If the boot mode header is missing or wrong, this could be a cause for an errant reset behavior.
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