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Darq1
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Hello,

The deviation is as follows:

"The simple test case of writing all 0 and checking for 1 should return a full bitmap.
However, in this device step, only one (the last) address of the SRAM is returned.
Workaround
Use the reverse test w1 - r0, which is working as expected and returns the full
bitmap."

I have trouble understanding what this errata deviation is describing. Could someone explain preferably in some examples what is the expected behavior, the actual behavior and the workaround?

Best regards

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Aiswarya_A
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25 likes received 250 sign-ins 50 solutions authored

Hello,

When a user wants to start a memory test, he/she has to configure the march sequence by the use of the CONFIG0 and CONFIG1 registers. In the CONFIG0 he/she has to configure the type of the access of each marching element.
The errata is basically saying that sequence w0-r1 (first march element writes 0 and second march element check for 1) is not working well.
Therefore it is suggested to use the sequence w1-r0 (first march element writes 1 and second march element check for 0).
You could refer to the description of the ACCSTYPE field of the MCi_CONFIG0 register in the AURIXTC3XX_um_part1_v2.0  User Manual.

Regards,
Aiswarya.

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Aiswarya_A
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25 likes received 250 sign-ins 50 solutions authored

Hi,

The extract from Errata sheet means that if you are writing 0s and checking for 1, ideally it should return every fault in the entire test address range. But here, it is returning fault only in the last address. As a workaround, program your test memory with 1s and read 0s so that the expected result is obtained.

You can refer to this code example.
You can also refer to the section "8.4.4 Operation Modes" from tc29xB_um_v1.3 User Manual.

 

Regards,
Aiswarya.

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Hello,

Still don't understand as it explained nothing. Writing 0 where? Checking for 1 where? Is RDBFL supposed to indicate which bits are flipped? Is this what is meant by the fail bitmap? The ETRR register should contain the fail address? 

If the memory range is filled with 0x0000 and there are multiple addresses with flipped single bits to for example 0x0001, then during reading the memory range, only the last address will be contained in ETRR register? Do RDBFL registers still contain full bitmap (0x0001)? How RDBFL registers correspond to ETRR registers when there are maximum 40 and 5 of them respectively?

In case the memory is filled with 0xFFFF and there are multiple addresses with flipped single bits to for example 0xFFFE, then during reading the memory range, all of the addresses with error are contained in ETRR registers? Do RDBFL registers still contain full bitmap (0x0001)? 

Best regards

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Aiswarya_A
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25 likes received 250 sign-ins 50 solutions authored

Hi, 
Writing 0 and checking for 1 in the test memory range.  The fail bit map is in RDBFL and the associated address is in ETRR (0). As long as no fail has occurred RDBFL contains the last read information and ETRR has no valid data.
Kindly refer to the descriptions of MBIST Control Register, MBIST Status Register, RDBFL Register in the User Manual. 
You can also refer to the Appnote given in the below link.

https://myicp.infineon.com/sites/microcontrollers-aurix_customer_doc/Lists/defaultdoclib/AURIX%20TC2...

Also, refer to the IfxMtu_runNonDestructiveInversionTest() function in the above-mentioned code example.

Regards,
Aiswarya.

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How can you write 0 and read 1? If you write 0 then you also read 0, when you write 1 you read 1. How the expected read value is set? Is it only applicable to tests performing operations on a whole range? What about single address mode? What is contained in the RDBFL when the fail has occurred?

All of those examples describe only one use case of Non-Destructive Inversion Test with one injected error.

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Darq1
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5 replies posted First question asked 5 sign-ins

Any response?

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Aiswarya_A
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25 likes received 250 sign-ins 50 solutions authored

Hello,

When a user wants to start a memory test, he/she has to configure the march sequence by the use of the CONFIG0 and CONFIG1 registers. In the CONFIG0 he/she has to configure the type of the access of each marching element.
The errata is basically saying that sequence w0-r1 (first march element writes 0 and second march element check for 1) is not working well.
Therefore it is suggested to use the sequence w1-r0 (first march element writes 1 and second march element check for 0).
You could refer to the description of the ACCSTYPE field of the MCi_CONFIG0 register in the AURIXTC3XX_um_part1_v2.0  User Manual.

Regards,
Aiswarya.

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