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AURIX™ Forum Discussions

Level 1
Level 1
I have some tasks will be assigned to 3 cores in TC297. CPU1 in TC297 has checker core for lockstep function, it can be used as safety core. I will split my task and put safety critical part running on it.
But the safety critical task will have communication with other cores(CPU0, CPU2),my question is how to assign RAM space for the communication and what safety solution I should take to protect the share memory area?
If any registers should be used for share memory dividing, how is the register set process? Which chater I should read in TC297 user manual?
Thank you~
1 Reply
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
Hi Jevins. I'm not sure what "share memory dividing" means, but here are some tips:

- Consider that although all RAM is ECC protected against hard and soft errors, the non-lockstep CPUs aren't - so you might consider adding something like a CRC to validate blocks of memory that are read or written by non-lockstep CPUs
- Make sure you are handling data cache correctly (or disabling data cache) so you don't have cache coherency issues
- You should be familiar with the Safety Manual, which calls out the Safety Mechanisms for ensuring Freedom From Interference
- I would get familiar with the Memory Protection System, which is described in the TriCore Architecture Manual (TC_Architecture_vol1_TC161_TCS_TC16P_TC16E.pdf)
- Also include Safety Memory Protection, which is described in the User Manual (5.12.6)