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User11554
Level 1
Level 1
Hi,

I am seeing a problem with /CS activating and clock not rising fast enough for the desired SPI mode. External logic analyzer (Saleae) says this is not according to norm:
Clock should be high, when /CS is going "active".



I tried the settings for
BACON LPRE and LEAD but the only result is, that to clock starts cycling later:



I know the signals are looking bad, but that´s nothing i can change without any change in hardware. We already have the padmode on "maximum speed".

What i would need:
Is there any setting i may have missed, to set the clock to high before /CS is actived.
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3 Replies
MoD
Employee
Employee
50 likes received 500 replies posted 100 solutions authored
Set the corresponding pins to speed grade 1 via register Pxx.PDRy, then you get the strong edges. The default value for the pins is speed grade 4/weak edge.
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User11554
Level 1
Level 1
As i said, we already set the pad speed to maximum speed.
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MoD
Employee
Employee
50 likes received 500 replies posted 100 solutions authored
It seems you expect that the idle level is high for SCLK. Set the CPOL bit in the used ECON register. As I known is the SPI normally edge driven (changing edge and sampling edge) and not level driven.
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