Not applicable
Aug 24, 2016
03:40 PM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Aug 24, 2016
03:40 PM
If these questions are answered in some document, please point me in that direction.
How much cache does each V1.6.1 core have ?
What is the "set association" of each V1.6.1 core ?
How big is a cache "line" ?
What is the width of the data portion of the SRI cross bar ?
Assuming no other resource on the SRI cross bar is blocking, how many cycles does it take to fill a cache line from the program Flash memory ?
How much RAM does the chip have, not including cache.?
How much cache does each V1.6.1 core have ?
What is the "set association" of each V1.6.1 core ?
How big is a cache "line" ?
What is the width of the data portion of the SRI cross bar ?
Assuming no other resource on the SRI cross bar is blocking, how many cycles does it take to fill a cache line from the program Flash memory ?
How much RAM does the chip have, not including cache.?
- Tags:
- IFX
1 Reply
Not applicable
Aug 31, 2016
06:41 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Aug 31, 2016
06:41 AM
Bump ! No one knows ? I am sure cache size is not proprietary !