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tripod
Level 1
Level 1
5 sign-ins First solution authored First reply posted

Hi all,

 

I am trying to confirm SRAM ECC enabled or disabled status by reading SRAM related ECCS register value. Under LAUTERBACH TRACE32 environment, after execution of code in Figure 1, below steps are manually operated.

tripod_0-1638364573136.png

 

Figure 1 Enable MTU module

 

1. Press Pause in TRACE. MTU_MEMTEST0.CPU0PTEN set Enable, press Run;

2. Press Pause, no Trap found.  MTU_MEMTEST0.CPU0PSEN, press Run;

3. MTU_MEMTEST0.CPU1PTEN set Enable and no Trap;

5. MTU_MEMTEST0.CPU1PSEN set Enable and no Trap;

6. MTU_MEMTEST0.CPU1DTEN set Enable and no Trap;

7. MTU_MEMTEST0.CPU1DSEN set Enable and no Trap;

8. MTU_MEMTEST0.CPU0DSEN set Enable and Enter Context Management Trap is found after Run and Pause;

 

I'm curious about the reason why the operation of setting CPU0DSEN leading to Trap. Then, I think there should be a right approach of enable CPU0DSEN.

 

Hope somebody share suggestion with me. Thanks very much !

 

Best Regards,

tripod

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1 Solution
Prudhvi
Moderator
Moderator
Moderator
50 solutions authored 250 sign-ins 10 likes given

Hello,

Are below points mentioned in the User manual (importantly highlighted one) taken care:

                                       Prudhvi_0-1651744229169.png

Regards,

Prudhvi.

View solution in original post

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4 Replies
MoD
Employee
Employee
250 sign-ins 25 likes received 50 solutions authored

When you set the MTU_MEMTEST0.CPU0DSEN the the complete DSPR0 will be initialized with 0, this means your context save area will be cleared and is no longer available. Therefore you get a context management trap.

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tripod
Level 1
Level 1
5 sign-ins First solution authored First reply posted

Hi Mod,

 

Thanks for your reply at first. 

From datasheet tc26x_um_v1.3.pdf, the core0 of tc26x is TC1.6E, and Context Save Areas (CSA) and addresses targeted by explicit context load/store instructions may be placed in DSPR only. And from my view, CSA is related to function calls, interrupts and traps. I have also tried enable MTU_MEMTEST0.CPU0DSEN in core1 but still failed. Is this mean MTU_MEMTEST0.CPU0DSEN cannot be set enable ?

Hope for your reply and thanks very much.

 

Regards,

tripod

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Prudhvi
Moderator
Moderator
Moderator
50 solutions authored 250 sign-ins 10 likes given

Hello,

Are below points mentioned in the User manual (importantly highlighted one) taken care:

                                       Prudhvi_0-1651744229169.png

Regards,

Prudhvi.

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tripod
Level 1
Level 1
5 sign-ins First solution authored First reply posted

Hi Prudhvi.,

Thanks for your reply. For the next step, the proper approach for enable MTU_MEMTEST0.CPU0DSEN needs some time to be found, avoiding tested memory.

Regards,

tripod

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