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abcmo123
Level 1
Level 1
5 questions asked 10 sign-ins 5 sign-ins

Dear Aurix users,

I notice the register bit RSTCON2.CSS0 is always zero after power on reset.

The follwing description is from TC234 user manual 

The RSTCON2.CSS bits indicate whether each CPU successfully flushed its write
buffers and reached an idle state before the previous reset. These bits can therefore be
used to determine whether RAM content integrity can be trusted after the previous reset
cycle.

It seems that the RAM did not successfully flush in our project.

abcmo123_0-1673489072344.png

 

I have no ideal that which  process shoud I do to make RSTCON2.CSS0 is 1 after power on reset.

Thanks.

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1 Solution
dw
Moderator
Moderator
Moderator
100 likes received 750 replies posted 10 likes given

After power on reset, it should be Zero.

But for warm reset, it maybe '1' or '0'. We use '1' to judge CPU0 is in safe state.

View solution in original post

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2 Replies
dw
Moderator
Moderator
Moderator
100 likes received 750 replies posted 10 likes given

After power on reset, it should be Zero.

But for warm reset, it maybe '1' or '0'. We use '1' to judge CPU0 is in safe state.

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abcmo123
Level 1
Level 1
5 questions asked 10 sign-ins 5 sign-ins

Dear dw,

Thank you for your reply.

I triggerd the warm reset in my project, and the RSTCON2.CSS0 showed the value "1".

 

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