At first pass you appear to have everything set correctly. What toolchain are you using?
If you put a breakpoint on your RX ISR and manually trigger the interrupt (SRCn.SETR = 1) do you go to the interrupt?
I don't use the illDs but here is my code for the QSPI3 (Master on the TC277 which would be the same for the TC234) if it helps using the HighTec free toolchain.
void QSPI3_Init(void)
{
uint16_t cpuWdtPassword = IfxScuWdt_getCpuWatchdogPassword();
IfxScuWdt_clearCpuEndinit(cpuWdtPassword);
QSPI3_CLC.U = 0x0; /* enable peripheral and allow sleep mode */
(void) QSPI3_CLC.U; /* read the register to force the write out of the cpu */
/* Kernel reset */
QSPI3_KRST0.U = 0x01;
QSPI3_KRST1.U = 0x01;
IfxScuWdt_setCpuEndinit(cpuWdtPassword);
/* wait for the kernel to be reset before proceeding */
while((QSPI3_KRST0.U & 0x02) != 0x02);
IfxScuWdt_clearCpuEndinit(cpuWdtPassword);
QSPI3_KRSTCLR.U = 0x01; /* Clear Reset done flag */
IfxScuWdt_setCpuEndinit(cpuWdtPassword);
/*
* The timing of the QSPI parameters are dependent on the input clock
* fBUAD2 is running at 200MHz
*/
/* GLOBALCON contains configuration parameters which affect all channels */
const Ifx_QSPI_GLOBALCON globalcon =
{
.B.TQ = 8, /* Global DIVIDER VALUE IS (TQ+1) */
.B.SI = qspi_globalcon_si_Disabled, /* Status Injection */
.B.EXPECT = qspi_globalcon_expect_1024, /* Time-Out Value for the Expect Phase */
.B.LB = qspi_globalcon_lb_Active, /* Loop-Back Control */
.B.DEL0 = qspi_globalcon_del0_Off, /* Delayed Mode for SLSO0 */
.B.STROBE = qspi_globalcon_strobe_NotUsed, /* Strobe Delay for SLSO0 in Delayed Mode */
.B.SRF = qspi_globalcon_srf_disabled, /* Stop on RxFIFO Full */
.B.STIP = qspi_globalcon_stip_NotUsed, /* Slave Transmit Idle State Polarity */
.B.EN = qspi_globalcon_en_PAUSE, /* Enable Bit */
.B.MS = qspi_globalcon_ms_MasterTransmitReceive, /* Master or Slave Mode */
.B.AREN = qspi_globalcon_aren_AutomaticResetEnabled, /* Automatic Reset Enable */
.B.RESETS = qspi_globalcon_resets_default /* Bits for resetting sub-modules per software */
};
QSPI3_GLOBALCON.U = globalcon.U;
/* GLOBALCON1 contains bit fields for control of the extension of the slave select signals by using an external demultiplexer */
const Ifx_QSPI_GLOBALCON1 globalcon1 =
{
.B.ERRORENS = qspi_globalcon1_errorens_AllErrorsEnabled, /* Error Enable Bits */
.B.TXEN = qspi_globalcon1_txen_InterruptEnabled, /* TX Interrupt Event Enable */
.B.RXEN = qspi_globalcon1_rxen_InterruptEnabled, /* RX Interrupt Event Enable */
.B.PT1EN = qspi_globalcon1_pt1en_InterruptDisabled, /* Interrupt on PT1 Event Enable */
.B.PT2EN = qspi_globalcon1_pt2en_InterruptDisabled, /* Interrupt on PT2 Event Enable */
.B.USREN = qspi_globalcon1_usren_InterruptDisabled, /* Interrupt on USR Event Enable */
.B.TXFIFOINT = qspi_globalcon1_txfifoint_Level2, /* Transmit FIFO Interrupt Threshold */
.B.RXFIFOINT = qspi_globalcon1_rxfifoint_Level1, /* Receive FIFO Interrupt Threshold */
.B.PT1 = qspi_globalcon1_pt1_EndOfWaitPhase, /* Phase Transition Event 1 */
.B.PT2 = qspi_globalcon1_pt2_EndOfWaitPhase, /* Phase Transition Event 2 */
.B.TXFM = qspi_globalcon1_txfm_SingleMoveMode, /* TXFIFO Mode */
.B.RXFM = qspi_globalcon1_rxfm_SingleMoveMode, /* RXFIFO Mode */
};
QSPI3_GLOBALCON1.U = globalcon1.U;
/* Defines the basic configuration parameters for the current slave select. It can be read by
* software, or written through a write to the TXFIFO.
*/
const Ifx_QSPI_BACON baconEntry =
{
.B.CS = 12, /* Slave Channel Select for timing */
.B.DL = 14, /* value = Data Length + 1 data bits */
.B.BYTE = qspi_baconEntry_byte_Bits, /* length in bits or bytes */
.B.MSB = qspi_baconEntry_Shift_LSB_first, /* Shift Mode */
.B.UINT = qspi_baconEntry_UserInterruptPT1_EventDisabled, /* User Interrupt at the PT1 Event in the Subsequent Frames */
.B.PARTYP = qspi_baconEntry_partyp_Even, /* Parity Type */
.B.TRAIL = 3, /* 2 Trailing Delay Length*/
.B.TPRE = 1, /* 3 Prescaler for the Trailing Delay */
.B.LEAD = 3, /* 2 Leading Delay Length */
.B.LPRE = 1, /* 3 Prescaler for the Leading Delay */
.B.IDLE = 0, /* 7 Idle Delay Length */
.B.IPRE = 5, /* 3 Prescaler for the Idle Delay */
.B.LAST = qspi_baconEntry_last_true, /* Last Word in a Frame */
};
QSPI3_BACONENTRY.U = baconEntry.U;
const Ifx_QSPI_ECON econ =
{
.B.Q = 3, /* DIVIDER VALUE IS (Q+1) */
.B.A = 1, /* DIVIDER VALUE IS (A+1) */
.B.B = 1, /* Length expressed in time quantum of ECONz.Q */
.B.C = 1, /* Length expressed in time quantum of ECONz.Q */
.B.CPH = qspi_econ_cph_0, /* Clock Phase (mandatory setting) */
.B.CPOL = qspi_econ_cpol_low, /* Clock Polarity (mandatory setting) */
.B.PAREN = qspi_econ_paren_Enabled, /* Enable Parity Check */
.B.BE = qspi_econ_be_SwapDisabled, /* Permutate bytes to / from Big Endian */
};
QSPI3_ECON4.U = econ.U;
const Ifx_QSPI_SSOC ssoc =
{
.B.OEN = qspi_ssoc_oen_slso12,
.B.AOL = qspi_ssoc_aol_none,
};
QSPI3_SSOC.U = ssoc.U;
const Ifx_QSPI_STATUS1 status1 =
{
.B.SPD = qspi_status1_SpikeDetectionNoEvent, /* Spike Detection Flag */
.B.SPDEN = qspi_status1_SpikeDetectionDisabled, /* Spike Detection Enable */
.B.BRD = qspi_status1_BaudRateDeviationNoEvent, /* Baud Rate Deviation Flag */
.B.BRDEN = qspi_status1_BaudRateDeviationDisabled, /* Baud Rate Deviation Enable */
};
QSPI3_STATUS1.U = status1.U;
#if 1 // use interrupt or polling
#if 0 // polling
/* Enter interrupt level and initialize both the SRC and table entry */
SRC_QSPI3RX.U = (CPU0_SERVICE << TOS) | (false << SRE) | INTPRIO_CPU0_QSPI3_RX;
SRC_QSPI3TX.U = (CPU0_SERVICE << TOS) | (false << SRE) | INTPRIO_CPU0_QSPI3_TX;
#else // interrupts
/* Enter interrupt level and initialize both the SRC and table entry */
SRC_QSPI3RX.U = (CPU0_SERVICE << TOS) | (true << SRE) | INTPRIO_CPU0_QSPI3_RX;
SRC_QSPI3TX.U = (CPU0_SERVICE << TOS) | (true << SRE) | INTPRIO_CPU0_QSPI3_TX;
#endif
#else // use DMA
SRC_QSPI3RX.U = (DMA_SERVICE << TOS) | (true << SRE) | DMA_CH6_QSPI3_RX;
SRC_QSPI3TX.U = (DMA_SERVICE << TOS) | (true << SRE) | DMA_CH5_QSPI3_TX;
#endif
IfxScuWdt_clearCpuEndinit(cpuWdtPassword);
/* select pins for the QSPI channel */
const Ifx_QSPI_PISEL pisel =
{
.B.MRIS = qspi_pisel_mris_mrstxE,
.B.SRIS = qspi_pisel_sris_mtsrxA,
.B.SCIS = qspi_pisel_scis_sclkxA,
.B.SLSIS = qspi_pisel_slsis_slsi_deselected,
};
QSPI3_PISEL.U = pisel.U;
/*
* P22.0 QSPI3 Master Transmit Output
* P22.1 QSPI3 Master Receive Input E
* P22.2 QSPI3 Slave Select Output 12 (ECON4)
* P22.3 QSPI3 Master Clock Output
*/
P22_IOCR0.B.PC0 = Port_PCx_Output_PushPull_Alt_3;
P22_IOCR0.B.PC1 = Port_PCx_Input_PullDown;
P22_IOCR0.B.PC2 = Port_PCx_Output_PushPull_Alt_3;
P22_IOCR0.B.PC3 = Port_PCx_Output_PushPull_Alt_3;
// Set the driver strength
P22_PDR0.U = Port_PDx_Speed_Grade_1;
IfxScuWdt_setCpuEndinit(cpuWdtPassword);
/* clear any pending interrupt */
SRC_QSPI3TX.B.CLRR = true;
/* Enable SPI with user configuration */
QSPI3_GLOBALCON.B.EN = qspi_globalcon_en_RUN;
/* set up data structures */
QSPI3_txHeadIdx = 0;
QSPI3_txTailIdx = 0;
QSPI3_rxHeadIdx = 0;
QSPI3_rxTailIdx = 0;
QSPI3_txSendCount = 0;
QSPI3_rxReceiveCount = 0;
}
/** \brief Service the Receive interrupt on the QSPI
*
* \param None
* \return Nothing
*/
IFX_INTERRUPT(QSPI3_RxISR, 0, INTPRIO_CPU0_QSPI3_RX);
void QSPI3_RxISR(void)
{
/* indicated to the software loop we have data waiting in the software receive buffer */
QSPI3_rxReceiveCount++;
/* read received data into the ring buffer clearing the CMD bit */
QSPI3_rxBuf[QSPI3_rxHeadIdx++] = (uint16_t) (QSPI3_RXEXIT.U);
/* increment the head pointer of the receive ring buffer */
QSPI3_rxHeadIdx = QSPI3_rxHeadIdx & (QSPI3_RXBUF_SIZE - 1);
}
/** \brief Service the Transmit interrupt on the QSPI
*
* \param None
* \return Nothing
*/
IFX_INTERRUPT(QSPI3_TxISR, 0, INTPRIO_CPU0_QSPI3_TX);
void QSPI3_TxISR(void)
{
/* Transmit interrupt flag handler */
if (QSPI3_txSendCount > 0)
{
QSPI3_txSendCount--;
QSPI3_DATAENTRY0.U = QSPI3_txBuf[QSPI3_txTailIdx++];
QSPI3_txTailIdx = QSPI3_txTailIdx & (QSPI3_TXBUF_SIZE - 1);
}
else
{
QSPI3_txBusy = false;
}
}
