AURIX™ Forum Discussions

[User20083]

Hi,

As title says, BIV is empty (0x0).

Interrupt is not being generated. Currently using iLLD_1_0_1_11_0 with hightec toolchain.

How do I update vector table?

Code is as follows.

// Module Header
#include "Cpu0_Main.h"

#include 
#include 

#include "../hsi_misc/IfxCpu.h"
#include "../hsi_misc/IfxScu_reg.h"
#include "../hsi_misc/IfxAsclin.h"
#include "../hsi_misc/IfxDts_Dts.h"
#include "../hsi_misc/IfxStm.h"
#include "../hsi_misc/Bsp.h"
#include "../hsi_misc/IfxScuWdt.h"
#include "../hsi_misc/IfxGpt12.h"


#define  SPB_FREQ           PLL_FREQUENCY/2
#define  PLL_FREQUENCY      200000000.0f

IfxStm_CompareConfig g_STMConf;                                 /* STM configuration structure                      */
void initSTM(void);
void Gpt12_T3_ISRHandler(void);

IFX_INTERRUPT(isrSTM, 0, ISR_PRIORITY_STM0);
// void __interrupt(ISR_PRIORITY_STM0) isrSTM(void);
IFX_INTERRUPT(Gpt12_T3_ISRHandler, 0, ISR_PRIORITY_T3);

void isrSTM(void)
{
    /* Update the compare register value that will trigger the next interrupt and toggle the LED */
    IfxStm_increaseCompare(&MODULE_STM0, g_STMConf.comparator, IfxStm_getTicksFromMicroseconds(&MODULE_STM0,1000u));
    while(1) {;}
}

void Gpt12_T3_ISRHandler(void)
{
    while(1) {;}
}

int main(void)
{

    // __mtcr(CPU_BIV, (uint32)__INTTAB_CPU(0));

    // Change watchdog timer value before timeout
   IfxScuWdt_changeCpuWatchdogReload(IfxScuWdt_getSafetyWatchdogPassword(),0xff00);

   // Disable the watchdog timers
   IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword());
   IfxScuWdt_disableSafetyWatchdog(IfxScuWdt_getSafetyWatchdogPassword());

   IfxScuCcu_Config clocks;
   IfxScuCcu_initConfig(&clocks);

   // Configure the PLL dividers
   IfxScuCcu_calculateSysPllDividers(&clocks,PLL_FREQUENCY);

   // Initialise CCU
   IfxScuCcu_init(&clocks);

   // Set SPB frequency
   IfxScuCcu_setSpbFrequency(PLL_FREQUENCY/4); // 50 Mhz

    // IfxCpu_enableInterrupts(); // Disab
   
    IfxStm_initCompareConfig(&g_STMConf);           /* Initialize the configuration structure with default values   */

    g_STMConf.triggerPriority = ISR_PRIORITY_STM0;   /* Set the priority of the interrupt                            */
    g_STMConf.typeOfService = IfxSrc_Tos_cpu0;      /* Set the service provider for the interrupts                  */
    g_STMConf.ticks = IfxStm_getTicksFromMicroseconds(&MODULE_STM0,1000u);               /* Set the number of ticks after which the timer triggers an
                                                     * interrupt for the first time                                 */
    IfxStm_initCompare(&MODULE_STM0, &g_STMConf);            /* Initialize the STM with the user configuration               */

    // Init the GPT12 module
    IfxGpt12_enableModule(&MODULE_GPT120);
    IfxGpt12_T3_run(&MODULE_GPT120, IfxGpt12_TimerRun_stop); //stop the timer just in case fixme
    IfxGpt12_setGpt1BlockPrescaler(&MODULE_GPT120,IfxGpt12_Gpt1BlockPrescaler_4);

    // Init T3 Timer
    IfxGpt12_T3_setMode(&MODULE_GPT120, IfxGpt12_Mode_timer); // Set Timer3 to timer mode
    IfxGpt12_T3_setTimerDirection(&MODULE_GPT120, IfxGpt12_TimerDirection_down);
    IfxGpt12_T3_setTimerPrescaler(&MODULE_GPT120, IfxGpt12_TimerInputPrescaler_8);
    IfxGpt12_T3_setTimerValue(&MODULE_GPT120, 0XFF00); // To load in Monittor_start();

    // Init the T3 interrupt
    volatile Ifx_SRC_SRCR *source_address = IfxGpt12_T3_getSrc(&MODULE_GPT120);            // Interrupt address
    IfxSrc_init(source_address, ISR_PROVIDER(INTERRUPT_T3), ISR_PRIORITY(INTERRUPT_T3));   // Init service request(CPU0..2)
    IfxSrc_enable(source_address);    

    IfxCpu_resetAndStartCounters(IfxCpu_CounterMode_normal);
    float T3_frequency = IfxGpt12_T3_getFrequency(&MODULE_GPT120);
    unsigned int reload_value = (uint16)((T3_frequency/1000000)*(500));
    IfxGpt12_T3_setTimerValue(&MODULE_GPT120,reload_value);
    IfxGpt12_T3_run(&MODULE_GPT120, IfxGpt12_TimerRun_start);

    // __enable();

    while (TRUE)
    {
      REGRESSION_RUN_STOP_PASS;
    }

    return 0;
}

[cwunder]

In the cstart file you should see a line like

    /* Load Base Address of Interrupt Vector Table. we will do this later in the program */
    __mtcr(CPU_BIV, (uint32)__INTTAB(0));

This will load the BIV register with the base address for the interrupt vector table for that CPU.

[NeMa_4793301]

Hi Fernandes. This is normally part of the Base Project template - see 0_Src\BaseSw\Infra\ssw\tc39b\Tricore\ifx_ssw_tc0.c:

static void __Core0_start(void)
{
    /* Update safety and cpu/safety watchdog reload values */
    /* Password value is read again, because there is chance that local variables may be overridden. */
    unsigned short cpuWdtPassword    = Ifx_Ssw_getCpuWatchdogPasswordInline(&MODULE_SCU.WDTCPU[0]);
    unsigned short safetyWdtPassword = Ifx_Ssw_getSafetyWatchdogPasswordInline();

    Ifx_Ssw_clearCpuEndinitInline(&MODULE_SCU.WDTCPU[0], cpuWdtPassword);

// other stuff
    /* Set A0 Pointer to access global variables with small data addressing */
    Ifx_Ssw_setAddressReg(a0, __SDATA1(0));

    /* These to be un commented if A8 and A9 are required to be initialized */
    Ifx_Ssw_setAddressReg(a8, __SDATA3(0));
    Ifx_Ssw_setAddressReg(a9, __SDATA4(0));

    /* Trap vector table initialization is necessary if it is not same as default value */
    Ifx_Ssw_MTCR(CPU_BTV, (unsigned int)__TRAPTAB(0));
    /* Base interrupt vector table initialized */
    Ifx_Ssw_MTCR(CPU_BIV, (unsigned int)__INTTAB(0));
    /* Interrupt stack pointer is configured */
    Ifx_Ssw_MTCR(CPU_ISP, (unsigned int)__ISTACK(0));

Did you follow the steps described in the Hightec app note to create your project?
https://free-entry-toolchain.hightec-rt.com/HighTec_Free_TriCore_Entry_Toolchain_Migration_Guide.pdf

You might also consider using the relatively new AURIX Development Studio.

[User20083]

Did you follow the steps described in the Hightec app note to create your project?
https://free-entry-toolchain.hightec...tion_Guide.pdf

I tried this but the link to BIFACES is broken. Infineon returns with "Server: sso.infineon.com
Unable to authenticate the user."

I am accustomed to Hightec now and would like to continue using it.

The __INTTAB_CPU funtion seems to be undefined although the compiler file contains :

    extern unsigned int __USTACK##cpu[];      /**< user stack end */            \
    extern unsigned int __ISTACK##cpu[];      /**< interrupt stack end */       \
    extern unsigned int __INTTAB_CPU##cpu[];  /**< Interrupt vector table */    \
    extern unsigned int __TRAPTAB_CPU##cpu[]; /**< trap table */                \
    extern unsigned int __CSA##cpu[];         /**< context save area 1 begin */ \
    extern unsigned int __CSA##cpu##_END[];   /**< context save area 1 begin */

#define __USTACK(cpu)      __USTACK##cpu
#define __ISTACK(cpu)      __ISTACK##cpu
#define __INTTAB_CPU(cpu)  __INTTAB_CPU##cpu
#define __TRAPTAB_CPU(cpu) __TRAPTAB_CPU##cpu
#define __CSA(cpu)         __CSA##cpu
#define __CSA_END(cpu)     __CSA##cpu##_END

/*Wrapper macros for the tool specific definitions */
#if defined(IFX_USE_SW_MANAGED_INT)
#define __INTTAB(cpu)      ((unsigned int)__INTTAB_CPU##cpu | (unsigned int)0x1FE0)
#else
#define __INTTAB(cpu)      __INTTAB_CPU##cpu
#endif /*defined(IFX_USE_SW_MANAGED_INT) */

#define __TRAPTAB(cpu)     __TRAPTAB_CPU##cpu

#define __SDATA1(cpu)      __A0_MEM
#define __SDATA2(cpu)      __A1_MEM
#define __SDATA3(cpu)      __A8_MEM
#define __SDATA4(cpu)      __A9_MEM

The startup file my program uses is the crt0-tc2x.S and the start codes are as follows:

_start:
	.code32
	j	_startaddr
	.align	2

_startaddr:

	mfcr	%d0,CORE_ID			# core ID
	and	%d1,%d0,7			# CORE_ID_MASK
	sh	%d2,%d1,3			#  * 8
	sh	%d1,%d1,2			#  * 4
	add	%d2,%d2,%d1			# offset for SCU_WDTCPUnCON0 reg =  * 12
	movh.a	%a2,hi:SCU_WDTCPU0CON0
	lea	%a2,[%a2]lo:SCU_WDTCPU0CON0
	mov.a	%a7,%d2
	add.a	%a7,%a2,%a7			# addr of SCU_WDTCPUnCON0

do_endinit_cpuN:
	ld.w	%d1,[%a7]0			# %d1 = *SCU_WDTCPUnCON0
	jz.t	%d1,1,endinit_done_cpuN		# einit is cleared, set it
	mov.aa	%a4,%a7
	jl	asm_set_endinit_xx		# %a4 is set to SCU_WDTCPUnCON0
endinit_done_cpuN:

	mfcr	%d0,CORE_ID			# core ID
	jz	%d0,do_endinit_s		# Safety WDT handled by CPU0
	j	init_stack_pointers

do_endinit_s:
	movh.a	%a4,hi:SCU_WDTSCON0
	lea	%a4,[%a4]lo:SCU_WDTSCON0
	ld.w	%d1,[%a4]0			# %d1 = *SCU_WDTSCON0
	jz.t	%d1,1,endinit_done_s		# einit is cleared, set it
	jl	asm_set_endinit_xx		# %a4 is set to SCU_WDTSCON0
endinit_done_s:
	movh.a	%a4,hi:SCU_WDTCPU0CON0
	lea	%a4,[%a4]lo:SCU_WDTCPU0CON0
	jl	asm_clear_endinit_xx		# %a4 is set to cpu0

init_stack_pointers:
	/*
	 * initialize user and interrupt stack pointers
	 */
	movh.a	%sp,hi:__USTACK			# load %sp
	lea	%sp,[%sp]lo:__USTACK
	movh	%d0,hi:__ISTACK			# load $isp
	addi	%d0,%d0,lo:__ISTACK
	mtcr	$isp,%d0
	isync

[User20083]

Resolved successfully using different linker file