Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

AURIX™ Forum Discussions

User17799
Level 2
Level 2
First like received
Does the DMA engine function in CAN boot mode?
0 Likes
3 Replies
cwunder
Employee
Employee
25 likes received 25 solutions authored 100 sign-ins
Simple answer, yes if you configure it (meaning your code that is downloaded and running)
0 Likes
User17799
Level 2
Level 2
First like received
Conditions:
PFLASH0_FSR: bit RPROIN is 1
bit RPRODIS = 0 (meaning read protection is installed and enabled)

FLASH_FCON; bit RPA is 1 (meaning protection is active),
bit DCF is 1 (Disable Code Fetch from Flash Memory, meaning code fetch is not allowed)
bit DDFDBG is 1 (Disable Data Fetch from Debug System, meaning data fetch is not allowed)
bit DDFDMA is 0 (Disable Data Fetch from DMA controller, meaning data fetch is allowed)
bit DDFPCP is 0 (Disable Data Fetch from PCP, meaning data fetch is allowed)

I have tried moving one byte from both PFLASH and SPRAM to a destination in SPRAM or the GPIO PORT0, the transfer appears to have completed however the destination remains unchanged.
I have the source address set for auto-increment and after the transfer completes the source address register has incremented.

Here is my code


int Init_DMA_xfer_first_byte()
{
// volatile unsigned int DummyToForceRead;

source_address = (unsigned int)0xd4000000; //point to PFLASH

// -----------------------------------------------------------------------
// Configuration of the DMA Module Clock: (not sure if anything needs to be done here)
// -----------------------------------------------------------------------
// - enable the DMA module

// MAIN_vResetENDINIT();
// DMA_CLC.U = 0x00000008; // DMA clock control register
// DummyToForceRead = DMA_CLC.U; // read it back to ensure it is read
// MAIN_vSetENDINIT();

// reset the DMA channel
DMA_CHRSTR = 1;
while(DMA_CHRSTR & 1) { // wait for channel to become ready
;
}

DMA_EER = 0x00000000; // enable error register
DMA_ME0PR = 0x00000000; // move engine 0 pattern register

// -----------------------------------------------------------------------
// Enabled Address Ranges For Move Engine 0:
// -----------------------------------------------------------------------
// - SCU incl. WDT, MEMCHK
// - SBCU
// - STM
// - OCDS
// - MSC0
// - ASC0
// - ASC1
// - P0, P1, P2, P3
// - P4, P5
// - GPTA0
// - DMA
// - MultiCAN
// - PCP Registers/Data Memory
// - PCP Code Memory
// - SSC0
// - FADC
// - ADC0
// - MLI0 Module/Tr. Windows
// - CPS, CPU SFRs/PGRs, PMU, Flash Regs, DMU, DBCU, DMI, PMI, PBCU, LFI
// - Program Flash Space
// - Data Flash Space
// - Emulation Device
// - Boot ROM
// - LMU Image (incl. OVRAM)
// - DMI Image
// - PMI Image

MAIN_vResetENDINIT();

// DMA_ME0AENR = 0xEEAB7FFF; // Access enable register, enable everything
DMA_ME0AENR = 0xFFFFFFFF; // Access enable register, enable everything

// - OVRAM address slice: 0xE8000000 - 0xE80001FF (512 Bytes)
// - DMI RAM address slice: 0xE8400000 - 0xE84001FF (512 Bytes)

DMA_ME0ARR = 0x00000000; // Access range register

MAIN_vSetENDINIT();

// -----------------------------------------------------------------------
// Configuration of DMA Channel 00:
// -----------------------------------------------------------------------
// - Hardware transfer: disabled
// - Number Of Moves Per Transaction: 1 Move
// - Transfer Reload Value: 1
// - Reset DMA Request After Each Transfer
// - Channel Operation Mode: Single Mode Operation
// - Channel Priority: High Priority
// - DMA Priority: High Priority
// - Pattern Select: Disabled
// - Channel Data Width: 8 Bits (Byte)

DMA_CHCR00 = 0x50000001; // Channel 00 control register
// DMA_CHCR00 = 1; // set dma transfer count and RROAT

DMA_SADR00 = source_address;
DMA_DADR00 = (unsigned int)&DMA_target[0];
// DMA_DADR00 = 0xF0000C00; // port 0 out

// - Source Modification Factor: Data Width * 1
// - Increment Control of Source Address: Increment
// - Circular Buffer Length Source: 2 Bytes
// - Destination Modification Factor: Data Width * 1
// - Increment Control of Destination Address: Decrement
// - Circular Buffer Length Destination: No Address Modification

DMA_ADRCR00 = 0x00000f08; // Channel 00 address control register

// - Transaction request lost for channel 00: disabled
// - The Wrap interrupt is not used
// - The Transfer/Pattern Match interrupt is not used
DMA_CHICR00 = 0x00000000; // Channel 00 interrupt control register

// -----------------------------------------------------------------------
// Channel Registers:
// -----------------------------------------------------------------------
DMA_HTREQ = 0x00010000; // Hardware transaction request register, may have to set to 0x00010000 - disable hardware channel 0

// -----------------------------------------------------------------------
// DMA Bus Time-Out:
// -----------------------------------------------------------------------
// - Bus time-out: 65535 cycles

DMA_TOCTR = 0x0000FFFF; // Bus time-out control register

DMA_STREQ = 1; // start channel zero

while((DMA_TRSR & 1)) { // while engine running
;
}
if(DMA_ERRSR) {
return(0);
}
return(1);
}
0 Likes
cwunder
Employee
Employee
25 likes received 25 solutions authored 100 sign-ins
The TC1766 is a legacy device and not recommend for new designs.

You have the source pointer set the SPRAM and the destination is DMA_target which no clue where you have this.

In addition you have the read protection on, I would suggest to debug the code with the Flash read protection off.

I have a TC1767 TriBoard with a setup to match most of your code. There are LEDs on P5 which are configured as output. The DMA channel 0 is set up to transfer Flash bytes to P5_OUT. When running the code you will see the LEDs updated by the bytes being read from the PFlash.

volatile unsigned int cnt;

void DMA_ChannelInit(void)
{
unlock_wdtcon();
DMA_ME0AENR.U = 0xFFFFFFFF; // Access enable register, enable everything
DMA_ME0ARR.U = 0x00000000; // Access range register
lock_wdtcon();


// -----------------------------------------------------------------------
// Configuration of DMA Channel 00:
// -----------------------------------------------------------------------
DMA_CHCR00_type chcr00 = {
.B.DMAPRIO = 0, // DMA Priority : Low
.B.CHPRIO = 0, // Channel Priority : low
.B.PATSEL = 0, // Pattern select disabled
.B.CHDW = 0, // Channel Data Width : 8-bit
.B.CHMODE = 0, // Channel OPeration Mode : Single Mode
.B.RROAT = 0, // Reset Request Only After Transaction
.B.BLKM = 0, // One DMA transfer has 1 DMA move
.B.PRSEL = 0, // Peripheral Request Select is not used
.B.TREL = 1, // number of DMA transfers for DMA transaction
};
DMA_CHCR00.U = chcr00.U;
DMA_SADR00.U = 0xA0000000; // source address is the PFlash
DMA_DADR00.U = (uint32) &P5_OUT.U; // destination address P5_OUT


DMA_ADRCR00_type adrcr00 = {
.B.SMF = 0, // Address offset is 1 x CHCR0x.CHDW
.B.INCS = 1, // Address offset will be added
.B.DMF = 0, // 000B Address offset is 1 x CHDW
.B.INCD = 0, // Address offset will be subtracted
.B.CBLS = 15, // Source address SADR[31:15] is not updated
.B.CBLD = 0, // Destination address DADR[31:0] is not updated
.B.SHCT = 0, // Shadow address register not used
.B.SHWEN = 0, // Shadow Address Register Write Enable
};
DMA_ADRCR00.U = adrcr00.U;
}


/* entry point from cstart */
void main(void)
{
// LEDs on P5[7:0]
P5_IOCR0.U = 0x80808080;
P5_IOCR4.U = 0x80808080;


// setup the DMA for Channel 0
DMA_ChannelInit();


while (1) {
for (cnt = 0x500000; cnt--;)
;
// trigger transfer
DMA_STREQ.U = 1;
}

}


3761.attach
0 Likes