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User18223
Level 1
Level 1
Hello,

I'm using TC275, and i have a variable located in cached LMU (shared RAM). I update sequentially it's value from core0 (TC1.6E), then core1 (TC1.6P), then core2 (TC1.6P) but only the first core was able to write into the LMU.
I tested the isync and dsync instructions after writing to that variable, but without effect.

Thanks to everybody,
best greetings!

AA.
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5 Replies
NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
Do you have data cache enabled? DSYNC will force the store buffers to complete, but it won't purge any writes that are lounging around in DCACHE.

Check CPUx_DCON0: if DCON0.DCBYP=0 (bit 2), data cache is enabled.

The TriCore doesn't have automatic cache coherency, so you have a few ways of forcing the write to become visible to other cores:
- Set CPUx_PMA0 to 0x100 instead of the default 0x300, so LMU data is not cached
- Use the uncached LMU addresses of 0xBxxxxxxx instead of 0x9xxxxxxx
- Invalidate the cache (see this thread: https://www.infineonforums.com/threads/2759-Cache-invalidation)
- Disable data cache
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User18223
Level 1
Level 1
Thank you for your answer.
Yes, The Dcache was enabled.

Should i understand that there is no way to flush Dcache content into the LMU so the only way is to use LMU no cached either by disabling the Dcache or changing the LMU attribute.
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NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
See the post I referenced - it is possible to purge the entire cache, or purge individual entries. The other alternatives are much easier.
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User18223
Level 1
Level 1
Still not solving the problem. My goal is to write into the cached LMU from TC1.6P core, the referenced post helps to flush the Dcache.
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NeMa_4793301
Level 6
Level 6
10 likes received 10 solutions authored 5 solutions authored
When you have data cache enabled, writes are not purged from the cache until they become the Least Recently Used entries.

Easy solutions include disabling data cache, turning off caching for LMU RAM, or using non-cached addressing for LMU.

Harder solutions include manually purging cache lines with the CACHEA instruction, or invalidating the entire data cache, both included in the previously referenced post.
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